| /* |
| * Device Tree Source for UniPhier Pro5 SoC |
| * |
| * Copyright (C) 2015-2016 Socionext Inc. |
| * Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
| * |
| * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| */ |
| |
| / { |
| compatible = "socionext,uniphier-pro5"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0>; |
| clocks = <&sys_clk 32>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| operating-points-v2 = <&cpu_opp>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <1>; |
| clocks = <&sys_clk 32>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| operating-points-v2 = <&cpu_opp>; |
| }; |
| }; |
| |
| cpu_opp: opp-table { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-116667000 { |
| opp-hz = /bits/ 64 <116667000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-150000000 { |
| opp-hz = /bits/ 64 <150000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-175000000 { |
| opp-hz = /bits/ 64 <175000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-233334000 { |
| opp-hz = /bits/ 64 <233334000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-350000000 { |
| opp-hz = /bits/ 64 <350000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-400000000 { |
| opp-hz = /bits/ 64 <400000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-466667000 { |
| opp-hz = /bits/ 64 <466667000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-600000000 { |
| opp-hz = /bits/ 64 <600000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-700000000 { |
| opp-hz = /bits/ 64 <700000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-800000000 { |
| opp-hz = /bits/ 64 <800000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-933334000 { |
| opp-hz = /bits/ 64 <933334000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-1200000000 { |
| opp-hz = /bits/ 64 <1200000000>; |
| clock-latency-ns = <300>; |
| }; |
| opp-1400000000 { |
| opp-hz = /bits/ 64 <1400000000>; |
| clock-latency-ns = <300>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| clocks { |
| refclk: ref { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <20000000>; |
| }; |
| |
| arm_timer_clk: arm-timer { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <50000000>; |
| }; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interrupt-parent = <&intc>; |
| |
| l2: l2-cache@500c0000 { |
| compatible = "socionext,uniphier-system-cache"; |
| reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, |
| <0x506c0000 0x400>; |
| interrupts = <0 190 4>, <0 191 4>; |
| cache-unified; |
| cache-size = <(2 * 1024 * 1024)>; |
| cache-sets = <512>; |
| cache-line-size = <128>; |
| cache-level = <2>; |
| next-level-cache = <&l3>; |
| }; |
| |
| l3: l3-cache@500c8000 { |
| compatible = "socionext,uniphier-system-cache"; |
| reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, |
| <0x506c8000 0x400>; |
| interrupts = <0 174 4>, <0 175 4>; |
| cache-unified; |
| cache-size = <(2 * 1024 * 1024)>; |
| cache-sets = <512>; |
| cache-line-size = <256>; |
| cache-level = <3>; |
| }; |
| |
| serial0: serial@54006800 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006800 0x40>; |
| interrupts = <0 33 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart0>; |
| clocks = <&peri_clk 0>; |
| resets = <&peri_rst 0>; |
| }; |
| |
| serial1: serial@54006900 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006900 0x40>; |
| interrupts = <0 35 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| clocks = <&peri_clk 1>; |
| resets = <&peri_rst 1>; |
| }; |
| |
| serial2: serial@54006a00 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006a00 0x40>; |
| interrupts = <0 37 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| clocks = <&peri_clk 2>; |
| resets = <&peri_rst 2>; |
| }; |
| |
| serial3: serial@54006b00 { |
| compatible = "socionext,uniphier-uart"; |
| status = "disabled"; |
| reg = <0x54006b00 0x40>; |
| interrupts = <0 177 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| clocks = <&peri_clk 3>; |
| resets = <&peri_rst 3>; |
| }; |
| |
| gpio: gpio@55000000 { |
| compatible = "socionext,uniphier-gpio"; |
| reg = <0x55000000 0x200>; |
| interrupt-parent = <&aidet>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl 0 0 0>; |
| gpio-ranges-group-names = "gpio_range"; |
| ngpios = <248>; |
| socionext,interrupt-ranges = <0 48 16>, <16 154 5>; |
| }; |
| |
| i2c0: i2c@58780000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58780000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 41 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0>; |
| clocks = <&peri_clk 4>; |
| resets = <&peri_rst 4>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c1: i2c@58781000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58781000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 42 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| clocks = <&peri_clk 5>; |
| resets = <&peri_rst 5>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c2: i2c@58782000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58782000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 43 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| clocks = <&peri_clk 6>; |
| resets = <&peri_rst 6>; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c3: i2c@58783000 { |
| compatible = "socionext,uniphier-fi2c"; |
| status = "disabled"; |
| reg = <0x58783000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 44 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| clocks = <&peri_clk 7>; |
| resets = <&peri_rst 7>; |
| clock-frequency = <100000>; |
| }; |
| |
| /* i2c4 does not exist */ |
| |
| /* chip-internal connection for DMD */ |
| i2c5: i2c@58785000 { |
| compatible = "socionext,uniphier-fi2c"; |
| reg = <0x58785000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 25 4>; |
| clocks = <&peri_clk 9>; |
| resets = <&peri_rst 9>; |
| clock-frequency = <400000>; |
| }; |
| |
| /* chip-internal connection for HDMI */ |
| i2c6: i2c@58786000 { |
| compatible = "socionext,uniphier-fi2c"; |
| reg = <0x58786000 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <0 26 4>; |
| clocks = <&peri_clk 10>; |
| resets = <&peri_rst 10>; |
| clock-frequency = <400000>; |
| }; |
| |
| system_bus: system-bus@58c00000 { |
| compatible = "socionext,uniphier-system-bus"; |
| status = "disabled"; |
| reg = <0x58c00000 0x400>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_system_bus>; |
| }; |
| |
| smpctrl@59801000 { |
| compatible = "socionext,uniphier-smpctrl"; |
| reg = <0x59801000 0x400>; |
| }; |
| |
| sdctrl@59810000 { |
| compatible = "socionext,uniphier-pro5-sdctrl", |
| "simple-mfd", "syscon"; |
| reg = <0x59810000 0x400>; |
| |
| sd_clk: clock { |
| compatible = "socionext,uniphier-pro5-sd-clock"; |
| #clock-cells = <1>; |
| }; |
| |
| sd_rst: reset { |
| compatible = "socionext,uniphier-pro5-sd-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| perictrl@59820000 { |
| compatible = "socionext,uniphier-pro5-perictrl", |
| "simple-mfd", "syscon"; |
| reg = <0x59820000 0x200>; |
| |
| peri_clk: clock { |
| compatible = "socionext,uniphier-pro5-peri-clock"; |
| #clock-cells = <1>; |
| }; |
| |
| peri_rst: reset { |
| compatible = "socionext,uniphier-pro5-peri-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| soc-glue@5f800000 { |
| compatible = "socionext,uniphier-pro5-soc-glue", |
| "simple-mfd", "syscon"; |
| reg = <0x5f800000 0x2000>; |
| |
| pinctrl: pinctrl { |
| compatible = "socionext,uniphier-pro5-pinctrl"; |
| }; |
| }; |
| |
| aidet: aidet@5fc20000 { |
| compatible = "socionext,uniphier-pro5-aidet"; |
| reg = <0x5fc20000 0x200>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| timer@60000200 { |
| compatible = "arm,cortex-a9-global-timer"; |
| reg = <0x60000200 0x20>; |
| interrupts = <1 11 0x304>; |
| clocks = <&arm_timer_clk>; |
| }; |
| |
| timer@60000600 { |
| compatible = "arm,cortex-a9-twd-timer"; |
| reg = <0x60000600 0x20>; |
| interrupts = <1 13 0x304>; |
| clocks = <&arm_timer_clk>; |
| }; |
| |
| intc: interrupt-controller@60001000 { |
| compatible = "arm,cortex-a9-gic"; |
| reg = <0x60001000 0x1000>, |
| <0x60000100 0x100>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| }; |
| |
| sysctrl@61840000 { |
| compatible = "socionext,uniphier-pro5-sysctrl", |
| "simple-mfd", "syscon"; |
| reg = <0x61840000 0x10000>; |
| |
| sys_clk: clock { |
| compatible = "socionext,uniphier-pro5-clock"; |
| #clock-cells = <1>; |
| }; |
| |
| sys_rst: reset { |
| compatible = "socionext,uniphier-pro5-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| nand: nand@68000000 { |
| compatible = "socionext,uniphier-denali-nand-v5b"; |
| status = "disabled"; |
| reg-names = "nand_data", "denali_reg"; |
| reg = <0x68000000 0x20>, <0x68100000 0x1000>; |
| interrupts = <0 65 4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_nand2cs>; |
| clocks = <&sys_clk 2>; |
| resets = <&sys_rst 2>; |
| }; |
| }; |
| }; |
| |
| #include "uniphier-pinctrl.dtsi" |
