| /* |
| * Copyright 2020 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #include "amdgpu.h" |
| #include "soc15.h" |
| |
| #include "gc/gc_9_4_2_offset.h" |
| #include "gc/gc_9_4_2_sh_mask.h" |
| #include "gfx_v9_0.h" |
| |
| #include "gfx_v9_4_2.h" |
| #include "amdgpu_ras.h" |
| #include "amdgpu_gfx.h" |
| |
| enum gfx_v9_4_2_utc_type { |
| VML2_MEM, |
| VML2_WALKER_MEM, |
| UTCL2_MEM, |
| ATC_L2_CACHE_2M, |
| ATC_L2_CACHE_32K, |
| ATC_L2_CACHE_4K |
| }; |
| |
| struct gfx_v9_4_2_utc_block { |
| enum gfx_v9_4_2_utc_type type; |
| uint32_t num_banks; |
| uint32_t num_ways; |
| uint32_t num_mem_blocks; |
| struct soc15_reg idx_reg; |
| struct soc15_reg data_reg; |
| uint32_t sec_count_mask; |
| uint32_t sec_count_shift; |
| uint32_t ded_count_mask; |
| uint32_t ded_count_shift; |
| uint32_t clear; |
| }; |
| |
| static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = { |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351), |
| }; |
| |
| static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_1[] = { |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369b), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x21f0a2fe), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x49), |
| }; |
| |
| static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = { |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xfffffeef, 0x10b0000), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_UTCL1_CNTL1, 0xffffffff, 0x30800400), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20), |
| }; |
| |
| static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev); |
| static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev); |
| |
| void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, |
| uint32_t die_id) |
| { |
| soc15_program_register_sequence(adev, |
| golden_settings_gc_9_4_2_alde, |
| ARRAY_SIZE(golden_settings_gc_9_4_2_alde)); |
| |
| /* apply golden settings per die */ |
| switch (die_id) { |
| case 0: |
| soc15_program_register_sequence(adev, |
| golden_settings_gc_9_4_2_alde_die_0, |
| ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0)); |
| break; |
| case 1: |
| soc15_program_register_sequence(adev, |
| golden_settings_gc_9_4_2_alde_die_1, |
| ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1)); |
| break; |
| default: |
| dev_warn(adev->dev, |
| "invalid die id %d, ignore channel fabricid remap settings\n", |
| die_id); |
| break; |
| } |
| |
| return; |
| } |
| |
| void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, |
| uint32_t first_vmid, |
| uint32_t last_vmid) |
| { |
| uint32_t data; |
| int i; |
| |
| mutex_lock(&adev->srbm_mutex); |
| |
| for (i = first_vmid; i < last_vmid; i++) { |
| data = 0; |
| soc15_grbm_select(adev, 0, 0, 0, i); |
| data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); |
| data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); |
| data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, |
| 0); |
| WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data); |
| } |
| |
| soc15_grbm_select(adev, 0, 0, 0, 0); |
| mutex_unlock(&adev->srbm_mutex); |
| } |
| |
| void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev) |
| { |
| u32 tmp; |
| |
| gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| |
| tmp = 0; |
| tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1); |
| WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp); |
| |
| tmp = 0; |
| tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1); |
| WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp); |
| |
| WREG32_SOC15(GC, 0, regDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); |
| tmp = 0; |
| tmp = REG_SET_FIELD(tmp, DIDT_SQ_THROTTLE_CTRL, PWRBRK_STALL_EN, 1); |
| WREG32_SOC15(GC, 0, regDIDT_IND_DATA, tmp); |
| |
| WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); |
| tmp = 0; |
| tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12); |
| WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp); |
| } |
| |
| static const struct soc15_reg_entry gfx_v9_4_2_edc_counter_regs[] = { |
| /* CPF */ |
| { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), 0, 1, 1 }, |
| /* CPC */ |
| { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 0, 1, 1 }, |
| /* GDS */ |
| { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 0, 1, 1 }, |
| /* RLC */ |
| { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), 0, 1, 1 }, |
| { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), 0, 1, 1 }, |
| /* SPI */ |
| { SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), 0, 8, 1 }, |
| /* SQC */ |
| { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), 0, 8, 7 }, |
| { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), 0, 8, 7 }, |
| { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), 0, 8, 7 }, |
| { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), 0, 8, 7 }, |
| /* SQ */ |
| { SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), 0, 8, 14 }, |
| /* TCP */ |
| { SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), 0, 8, 14 }, |
| /* TCI */ |
| { SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), 0, 1, 69 }, |
| /* TCC */ |
| { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), 0, 1, 16 }, |
| { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), 0, 1, 16 }, |
| /* TCA */ |
| { SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), 0, 1, 2 }, |
| /* TCX */ |
| { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), 0, 1, 2 }, |
| { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), 0, 1, 2 }, |
| /* TD */ |
| { SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), 0, 8, 14 }, |
| /* TA */ |
| { SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), 0, 8, 14 }, |
| /* GCEA */ |
| { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), 0, 1, 16 }, |
| { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), 0, 1, 16 }, |
| { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 1, 16 }, |
| }; |
| |
| static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num, |
| u32 sh_num, u32 instance) |
| { |
| u32 data; |
| |
| if (instance == 0xffffffff) |
| data = REG_SET_FIELD(0, GRBM_GFX_INDEX, |
| INSTANCE_BROADCAST_WRITES, 1); |
| else |
| data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, |
| instance); |
| |
| if (se_num == 0xffffffff) |
| data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, |
| 1); |
| else |
| data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); |
| |
| if (sh_num == 0xffffffff) |
| data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, |
| 1); |
| else |
| data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); |
| |
| WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data); |
| } |
| |
| static const struct soc15_ras_field_entry gfx_v9_4_2_ras_fields[] = { |
| /* CPF */ |
| { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), |
| SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2), |
| SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) }, |
| { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), |
| SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1), |
| SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) }, |
| { "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), |
| SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), |
| SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) }, |
| |
| /* CPC */ |
| { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), |
| SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), |
| SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) }, |
| { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), |
| SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), |
| SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) }, |
| { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), |
| SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1), |
| SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) }, |
| { "CPC_DC_CSINVOC_RAM_ME1", |
| SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), |
| SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1), |
| SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) }, |
| { "CPC_DC_RESTORE_RAM_ME1", |
| SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), |
| SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1), |
| SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) }, |
| { "CPC_DC_CSINVOC_RAM1_ME1", |
| SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), |
| SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1), |
| SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) }, |
| { "CPC_DC_RESTORE_RAM1_ME1", |
| SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), |
| SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1), |
| SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) }, |
| |
| /* GDS */ |
| { "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), |
| SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC), |
| SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) }, |
| { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), |
| SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) }, |
| { "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) }, |
| { "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) }, |
| { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) }, |
| { "GDS_ME1_PIPE0_PIPE_MEM", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) }, |
| { "GDS_ME1_PIPE1_PIPE_MEM", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) }, |
| { "GDS_ME1_PIPE2_PIPE_MEM", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) }, |
| { "GDS_ME1_PIPE3_PIPE_MEM", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), |
| SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) }, |
| { "GDS_ME0_GFXHP3D_PIX_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_PIX_DED) }, |
| { "GDS_ME0_GFXHP3D_VTX_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_VTX_DED) }, |
| { "GDS_ME0_CS_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_CS_DED) }, |
| { "GDS_ME0_GFXHP3D_GS_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_GS_DED) }, |
| { "GDS_ME1_PIPE0_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE0_DED) }, |
| { "GDS_ME1_PIPE1_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE1_DED) }, |
| { "GDS_ME1_PIPE2_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE2_DED) }, |
| { "GDS_ME1_PIPE3_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE3_DED) }, |
| { "GDS_ME2_PIPE0_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE0_DED) }, |
| { "GDS_ME2_PIPE1_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE1_DED) }, |
| { "GDS_ME2_PIPE2_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE2_DED) }, |
| { "GDS_ME2_PIPE3_DED", |
| SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0, |
| SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE3_DED) }, |
| |
| /* RLC */ |
| { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) }, |
| { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) }, |
| { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) }, |
| { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) }, |
| { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) }, |
| { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) }, |
| { "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) }, |
| |
| /* SPI */ |
| { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) }, |
| { "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) }, |
| { "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) }, |
| { "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT), |
| SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) }, |
| |
| /* SQC - regSQC_EDC_CNT */ |
| { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) }, |
| { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) }, |
| { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) }, |
| { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) }, |
| { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) }, |
| { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) }, |
| { "SQC_DATA_CU3_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_DED_COUNT) }, |
| { "SQC_DATA_CU3_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_DED_COUNT) }, |
| |
| /* SQC - regSQC_EDC_CNT2 */ |
| { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) }, |
| { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) }, |
| { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) }, |
| { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) }, |
| { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) }, |
| { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT) }, |
| |
| /* SQC - regSQC_EDC_CNT3 */ |
| { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) }, |
| { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) }, |
| { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) }, |
| { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) }, |
| { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT) }, |
| |
| /* SQC - regSQC_EDC_PARITY_CNT3 */ |
| { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) }, |
| { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_DED_COUNT) }, |
| { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) }, |
| { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_DED_COUNT) }, |
| { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) }, |
| { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_DED_COUNT) }, |
| { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) }, |
| { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_DED_COUNT) }, |
| |
| /* SQ */ |
| { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) }, |
| { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) }, |
| { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) }, |
| { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) }, |
| { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) }, |
| { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) }, |
| { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), |
| SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) }, |
| |
| /* TCP */ |
| { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) }, |
| { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) }, |
| { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) }, |
| { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) }, |
| { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_DED_COUNT) }, |
| { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) }, |
| { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), |
| SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) }, |
| |
| /* TCI */ |
| { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), |
| SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) }, |
| |
| /* TCC */ |
| { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) }, |
| { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) }, |
| { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) }, |
| { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) }, |
| { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) }, |
| { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) }, |
| { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) }, |
| { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) }, |
| { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) }, |
| { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) }, |
| { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) }, |
| { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) }, |
| { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) }, |
| { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) }, |
| { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT), |
| SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) }, |
| |
| /* TCA */ |
| { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), |
| SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) }, |
| { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), |
| SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) }, |
| |
| /* TCX */ |
| { "TCX_GROUP0", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_SEC_COUNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_DED_COUNT) }, |
| { "TCX_GROUP1", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_SEC_COUNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_DED_COUNT) }, |
| { "TCX_GROUP2", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_SEC_COUNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_DED_COUNT) }, |
| { "TCX_GROUP3", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_SEC_COUNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_DED_COUNT) }, |
| { "TCX_GROUP4", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_SEC_COUNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_DED_COUNT) }, |
| { "TCX_GROUP5", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP5_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP6", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP6_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP7", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP7_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP8", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP8_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP9", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP9_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP10", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), |
| SOC15_REG_FIELD(TCX_EDC_CNT, GROUP10_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP11", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), |
| SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP11_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP12", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), |
| SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP12_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP13", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), |
| SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP13_SED_COUNT), 0, 0 }, |
| { "TCX_GROUP14", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), |
| SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP14_SED_COUNT), 0, 0 }, |
| |
| /* TD */ |
| { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), |
| SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), |
| SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) }, |
| { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), |
| SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), |
| SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) }, |
| { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), |
| SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) }, |
| |
| /* TA */ |
| { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) }, |
| { "TA_FS_AFIFO_LO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_SEC_COUNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_DED_COUNT) }, |
| { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) }, |
| { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) }, |
| { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) }, |
| { "TA_FS_AFIFO_HI", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_SEC_COUNT), |
| SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_DED_COUNT) }, |
| |
| /* EA - regGCEA_EDC_CNT */ |
| { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) }, |
| { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) }, |
| { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) }, |
| { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) }, |
| { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) }, |
| { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_DED_COUNT) }, |
| { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 }, |
| { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 }, |
| { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 }, |
| { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 }, |
| |
| /* EA - regGCEA_EDC_CNT2 */ |
| { "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) }, |
| { "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) }, |
| { "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) }, |
| { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 }, |
| { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 }, |
| { "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) }, |
| { "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) }, |
| { "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) }, |
| { "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) }, |
| |
| /* EA - regGCEA_EDC_CNT3 */ |
| { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) }, |
| { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) }, |
| { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) }, |
| { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) }, |
| { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) }, |
| { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0, |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) }, |
| { "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) }, |
| { "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) }, |
| { "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) }, |
| { "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) }, |
| { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_SEC_COUNT), |
| SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) }, |
| }; |
| |
| static const char * const vml2_walker_mems[] = { |
| "UTC_VML2_CACHE_PDE0_MEM0", |
| "UTC_VML2_CACHE_PDE0_MEM1", |
| "UTC_VML2_CACHE_PDE1_MEM0", |
| "UTC_VML2_CACHE_PDE1_MEM1", |
| "UTC_VML2_CACHE_PDE2_MEM0", |
| "UTC_VML2_CACHE_PDE2_MEM1", |
| "UTC_VML2_RDIF_ARADDRS", |
| "UTC_VML2_RDIF_LOG_FIFO", |
| "UTC_VML2_QUEUE_REQ", |
| "UTC_VML2_QUEUE_RET", |
| }; |
| |
| static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = { |
| { VML2_MEM, 8, 2, 2, |
| { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_INDEX) }, |
| { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_CNTL) }, |
| SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, SEC_COUNT), |
| SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, DED_COUNT), |
| REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) }, |
| { VML2_WALKER_MEM, ARRAY_SIZE(vml2_walker_mems), 1, 1, |
| { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_INDEX) }, |
| { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_CNTL) }, |
| SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, SEC_COUNT), |
| SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, DED_COUNT), |
| REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) }, |
| { UTCL2_MEM, 18, 1, 2, |
| { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_INDEX) }, |
| { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_CNTL) }, |
| SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, SEC_COUNT), |
| SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, DED_COUNT), |
| REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) }, |
| { ATC_L2_CACHE_2M, 8, 2, 1, |
| { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_INDEX) }, |
| { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_CNTL) }, |
| SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, SEC_COUNT), |
| SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, DED_COUNT), |
| REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) }, |
| { ATC_L2_CACHE_32K, 8, 2, 2, |
| { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_INDEX) }, |
| { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_CNTL) }, |
| SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, SEC_COUNT), |
| SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, DED_COUNT), |
| REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) }, |
| { ATC_L2_CACHE_4K, 8, 2, 8, |
| { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_INDEX) }, |
| { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_CNTL) }, |
| SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, SEC_COUNT), |
| SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, DED_COUNT), |
| REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) }, |
| }; |
| |
| static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs = |
| { SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 }; |
| |
| static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev, |
| const struct soc15_reg_entry *reg, |
| uint32_t se_id, uint32_t inst_id, |
| uint32_t value, uint32_t *sec_count, |
| uint32_t *ded_count) |
| { |
| uint32_t i; |
| uint32_t sec_cnt, ded_cnt; |
| |
| for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_ras_fields); i++) { |
| if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset || |
| gfx_v9_4_2_ras_fields[i].seg != reg->seg || |
| gfx_v9_4_2_ras_fields[i].inst != reg->inst) |
| continue; |
| |
| sec_cnt = SOC15_RAS_REG_FIELD_VAL( |
| value, gfx_v9_4_2_ras_fields[i], sec); |
| if (sec_cnt) { |
| dev_info(adev->dev, |
| "GFX SubBlock %s, Instance[%d][%d], SEC %d\n", |
| gfx_v9_4_2_ras_fields[i].name, se_id, inst_id, |
| sec_cnt); |
| *sec_count += sec_cnt; |
| } |
| |
| ded_cnt = SOC15_RAS_REG_FIELD_VAL( |
| value, gfx_v9_4_2_ras_fields[i], ded); |
| if (ded_cnt) { |
| dev_info(adev->dev, |
| "GFX SubBlock %s, Instance[%d][%d], DED %d\n", |
| gfx_v9_4_2_ras_fields[i].name, se_id, inst_id, |
| ded_cnt); |
| *ded_count += ded_cnt; |
| } |
| } |
| |
| return 0; |
| } |
| |
| static int gfx_v9_4_2_query_sram_edc_count(struct amdgpu_device *adev, |
| uint32_t *sec_count, uint32_t *ded_count) |
| { |
| uint32_t i, j, k, data; |
| uint32_t sec_cnt = 0, ded_cnt = 0; |
| |
| if (sec_count && ded_count) { |
| *sec_count = 0; |
| *ded_count = 0; |
| } |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| |
| for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_edc_counter_regs); i++) { |
| for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) { |
| for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance; |
| k++) { |
| gfx_v9_4_2_select_se_sh(adev, j, 0, k); |
| |
| /* if sec/ded_count is null, just clear counter */ |
| if (!sec_count || !ded_count) { |
| WREG32(SOC15_REG_ENTRY_OFFSET( |
| gfx_v9_4_2_edc_counter_regs[i]), 0); |
| continue; |
| } |
| |
| data = RREG32(SOC15_REG_ENTRY_OFFSET( |
| gfx_v9_4_2_edc_counter_regs[i])); |
| |
| if (!data) |
| continue; |
| |
| gfx_v9_4_2_get_reg_error_count(adev, |
| &gfx_v9_4_2_edc_counter_regs[i], |
| j, k, data, &sec_cnt, &ded_cnt); |
| |
| /* clear counter after read */ |
| WREG32(SOC15_REG_ENTRY_OFFSET( |
| gfx_v9_4_2_edc_counter_regs[i]), 0); |
| } |
| } |
| } |
| |
| if (sec_count && ded_count) { |
| *sec_count += sec_cnt; |
| *ded_count += ded_cnt; |
| } |
| |
| gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| |
| return 0; |
| } |
| |
| static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev, |
| struct gfx_v9_4_2_utc_block *blk, |
| uint32_t instance, uint32_t sec_cnt, |
| uint32_t ded_cnt) |
| { |
| uint32_t bank, way, mem; |
| static const char *vml2_way_str[] = { "BIGK", "4K" }; |
| static const char *utcl2_rounter_str[] = { "VMC", "APT" }; |
| |
| mem = instance % blk->num_mem_blocks; |
| way = (instance / blk->num_mem_blocks) % blk->num_ways; |
| bank = instance / (blk->num_mem_blocks * blk->num_ways); |
| |
| switch (blk->type) { |
| case VML2_MEM: |
| dev_info( |
| adev->dev, |
| "GFX SubBlock UTC_VML2_BANK_CACHE_%d_%s_MEM%d, SED %d, DED %d\n", |
| bank, vml2_way_str[way], mem, sec_cnt, ded_cnt); |
| break; |
| case VML2_WALKER_MEM: |
| dev_info(adev->dev, "GFX SubBlock %s, SED %d, DED %d\n", |
| vml2_walker_mems[bank], sec_cnt, ded_cnt); |
| break; |
| case UTCL2_MEM: |
| dev_info( |
| adev->dev, |
| "GFX SubBlock UTCL2_ROUTER_IFIF%d_GROUP0_%s, SED %d, DED %d\n", |
| bank, utcl2_rounter_str[mem], sec_cnt, ded_cnt); |
| break; |
| case ATC_L2_CACHE_2M: |
| dev_info( |
| adev->dev, |
| "GFX SubBlock UTC_ATCL2_CACHE_2M_BANK%d_WAY%d_MEM, SED %d, DED %d\n", |
| bank, way, sec_cnt, ded_cnt); |
| break; |
| case ATC_L2_CACHE_32K: |
| dev_info( |
| adev->dev, |
| "GFX SubBlock UTC_ATCL2_CACHE_32K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n", |
| bank, way, mem, sec_cnt, ded_cnt); |
| break; |
| case ATC_L2_CACHE_4K: |
| dev_info( |
| adev->dev, |
| "GFX SubBlock UTC_ATCL2_CACHE_4K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n", |
| bank, way, mem, sec_cnt, ded_cnt); |
| break; |
| } |
| } |
| |
| static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev, |
| uint32_t *sec_count, |
| uint32_t *ded_count) |
| { |
| uint32_t i, j, data; |
| uint32_t sec_cnt, ded_cnt; |
| uint32_t num_instances; |
| struct gfx_v9_4_2_utc_block *blk; |
| |
| if (sec_count && ded_count) { |
| *sec_count = 0; |
| *ded_count = 0; |
| } |
| |
| for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_utc_blocks); i++) { |
| blk = &gfx_v9_4_2_utc_blocks[i]; |
| num_instances = |
| blk->num_banks * blk->num_ways * blk->num_mem_blocks; |
| for (j = 0; j < num_instances; j++) { |
| WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j); |
| |
| /* if sec/ded_count is NULL, just clear counter */ |
| if (!sec_count || !ded_count) { |
| WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), |
| blk->clear); |
| continue; |
| } |
| |
| data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg)); |
| if (!data) |
| continue; |
| |
| sec_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, sec); |
| *sec_count += sec_cnt; |
| ded_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, ded); |
| *ded_count += ded_cnt; |
| |
| /* clear counter after read */ |
| WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), |
| blk->clear); |
| |
| /* print the edc count */ |
| if (sec_cnt || ded_cnt) |
| gfx_v9_4_2_log_utc_edc_count(adev, blk, j, sec_cnt, |
| ded_cnt); |
| } |
| } |
| |
| return 0; |
| } |
| |
| int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, |
| void *ras_error_status) |
| { |
| struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; |
| uint32_t sec_count = 0, ded_count = 0; |
| |
| if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
| return -EINVAL; |
| |
| err_data->ue_count = 0; |
| err_data->ce_count = 0; |
| |
| gfx_v9_4_2_query_sram_edc_count(adev, &sec_count, &ded_count); |
| err_data->ce_count += sec_count; |
| err_data->ue_count += ded_count; |
| |
| gfx_v9_4_2_query_utc_edc_count(adev, &sec_count, &ded_count); |
| err_data->ce_count += sec_count; |
| err_data->ue_count += ded_count; |
| |
| return 0; |
| } |
| |
| static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev) |
| { |
| WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3); |
| WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3); |
| WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3); |
| } |
| |
| static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev) |
| { |
| uint32_t i, j; |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { |
| for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance; |
| j++) { |
| gfx_v9_4_2_select_se_sh(adev, i, 0, j); |
| WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10); |
| } |
| } |
| gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| } |
| |
| void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) |
| { |
| if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
| return; |
| |
| gfx_v9_4_2_query_sram_edc_count(adev, NULL, NULL); |
| gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL); |
| } |
| |
| int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if) |
| { |
| struct ras_inject_if *info = (struct ras_inject_if *)inject_if; |
| int ret; |
| struct ta_ras_trigger_error_input block_info = { 0 }; |
| |
| if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
| return -EINVAL; |
| |
| block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); |
| block_info.sub_block_index = info->head.sub_block_index; |
| block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); |
| block_info.address = info->address; |
| block_info.value = info->value; |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| ret = psp_ras_trigger_error(&adev->psp, &block_info); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| |
| return ret; |
| } |
| |
| static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev) |
| { |
| uint32_t i, j; |
| uint32_t reg_value; |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| |
| for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { |
| for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance; |
| j++) { |
| gfx_v9_4_2_select_se_sh(adev, i, 0, j); |
| reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( |
| gfx_v9_4_2_ea_err_status_regs)); |
| if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || |
| REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || |
| REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { |
| dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n", |
| j, reg_value); |
| } |
| /* clear after read */ |
| WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10); |
| } |
| } |
| |
| gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| } |
| |
| static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev) |
| { |
| uint32_t data; |
| |
| data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS); |
| if (data) { |
| dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); |
| WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3); |
| } |
| |
| data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS); |
| if (data) { |
| dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); |
| WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3); |
| } |
| |
| data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS); |
| if (data) { |
| dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); |
| WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3); |
| } |
| } |
| |
| void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) |
| { |
| if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
| return; |
| |
| gfx_v9_4_2_query_ea_err_status(adev); |
| gfx_v9_4_2_query_utc_err_status(adev); |
| gfx_v9_4_2_query_sq_timeout_status(adev); |
| } |
| |
| void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) |
| { |
| if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) |
| return; |
| |
| gfx_v9_4_2_reset_utc_err_status(adev); |
| gfx_v9_4_2_reset_ea_err_status(adev); |
| gfx_v9_4_2_reset_sq_timeout_status(adev); |
| } |
| |
| void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev) |
| { |
| uint32_t i; |
| uint32_t data; |
| |
| data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, |
| amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : |
| 0); |
| |
| if (amdgpu_watchdog_timer.timeout_fatal_disable && |
| (amdgpu_watchdog_timer.period < 1 || |
| amdgpu_watchdog_timer.period > 0x23)) { |
| dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); |
| amdgpu_watchdog_timer.period = 0x23; |
| } |
| data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, |
| amdgpu_watchdog_timer.period); |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
| gfx_v9_4_2_select_se_sh(adev, i, 0xffffffff, 0xffffffff); |
| WREG32_SOC15(GC, 0, regSQ_TIMEOUT_CONFIG, data); |
| } |
| gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| } |
| |
| static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) |
| { |
| WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX, |
| (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | |
| (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | |
| (address << SQ_IND_INDEX__INDEX__SHIFT) | |
| (SQ_IND_INDEX__FORCE_READ_MASK)); |
| return RREG32_SOC15(GC, 0, regSQ_IND_DATA); |
| } |
| |
| static void gfx_v9_4_2_log_cu_timeout_status(struct amdgpu_device *adev, |
| uint32_t status) |
| { |
| struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; |
| uint32_t i, simd, wave; |
| uint32_t wave_status; |
| uint32_t wave_pc_lo, wave_pc_hi; |
| uint32_t wave_exec_lo, wave_exec_hi; |
| uint32_t wave_inst_dw0, wave_inst_dw1; |
| uint32_t wave_ib_sts; |
| |
| for (i = 0; i < 32; i++) { |
| if (!((i << 1) & status)) |
| continue; |
| |
| simd = i / cu_info->max_waves_per_simd; |
| wave = i % cu_info->max_waves_per_simd; |
| |
| wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); |
| wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); |
| wave_pc_hi = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); |
| wave_exec_lo = |
| wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); |
| wave_exec_hi = |
| wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); |
| wave_inst_dw0 = |
| wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); |
| wave_inst_dw1 = |
| wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); |
| wave_ib_sts = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); |
| |
| dev_info( |
| adev->dev, |
| "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", |
| simd, wave, wave_status, |
| ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), |
| ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), |
| ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), |
| wave_ib_sts); |
| } |
| } |
| |
| static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev) |
| { |
| uint32_t se_idx, sh_idx, cu_idx; |
| uint32_t status; |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; |
| se_idx++) { |
| for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; |
| sh_idx++) { |
| for (cu_idx = 0; |
| cu_idx < adev->gfx.config.max_cu_per_sh; |
| cu_idx++) { |
| gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx, |
| cu_idx); |
| status = RREG32_SOC15(GC, 0, |
| regSQ_TIMEOUT_STATUS); |
| if (status != 0) { |
| dev_info( |
| adev->dev, |
| "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", |
| se_idx, sh_idx, cu_idx); |
| gfx_v9_4_2_log_cu_timeout_status( |
| adev, status); |
| } |
| /* clear old status */ |
| WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0); |
| } |
| } |
| } |
| gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| } |
| |
| static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev) |
| { |
| uint32_t se_idx, sh_idx, cu_idx; |
| |
| mutex_lock(&adev->grbm_idx_mutex); |
| for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; |
| se_idx++) { |
| for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; |
| sh_idx++) { |
| for (cu_idx = 0; |
| cu_idx < adev->gfx.config.max_cu_per_sh; |
| cu_idx++) { |
| gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx, |
| cu_idx); |
| WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0); |
| } |
| } |
| } |
| gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
| mutex_unlock(&adev->grbm_idx_mutex); |
| } |
| |
| const struct amdgpu_gfx_ras_funcs gfx_v9_4_2_ras_funcs = { |
| .ras_late_init = amdgpu_gfx_ras_late_init, |
| .ras_fini = amdgpu_gfx_ras_fini, |
| .ras_error_inject = &gfx_v9_4_2_ras_error_inject, |
| .query_ras_error_count = &gfx_v9_4_2_query_ras_error_count, |
| .reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count, |
| .query_ras_error_status = &gfx_v9_4_2_query_ras_error_status, |
| .reset_ras_error_status = &gfx_v9_4_2_reset_ras_error_status, |
| .enable_watchdog_timer = &gfx_v9_4_2_enable_watchdog_timer, |
| }; |
