Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 MIPI D-PHY Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 0

  compatible:
    oneOf:
      - const: allwinner,sun6i-a31-mipi-dphy
      - const: allwinner,sun50i-a100-mipi-dphy
      - items:
          - const: allwinner,sun50i-a64-mipi-dphy
          - const: allwinner,sun6i-a31-mipi-dphy
      - items:
          - const: allwinner,sun20i-d1-mipi-dphy
          - const: allwinner,sun50i-a100-mipi-dphy

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: bus
      - const: mod

  resets:
    maxItems: 1

  allwinner,direction:
    $ref: /schemas/types.yaml#/definitions/string
    description: |
      Direction of the D-PHY:
      - "rx" for receiving (e.g. when used with MIPI CSI-2);
      - "tx" for transmitting (e.g. when used with MIPI DSI).

    enum:
      - tx
      - rx
    default: tx

required:
  - "#phy-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dphy0: d-phy@1ca1000 {
        compatible = "allwinner,sun6i-a31-mipi-dphy";
        reg = <0x01ca1000 0x1000>;
        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu 23>, <&ccu 97>;
        clock-names = "bus", "mod";
        resets = <&ccu 4>;
        #phy-cells = <0>;
    };

...