| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| * Copyright (C) 2019 reMarkable AS - http://www.remarkable.com/ |
| * |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx7d.dtsi" |
| |
| / { |
| model = "reMarkable 2.0"; |
| compatible = "remarkable,imx7d-remarkable2", "fsl,imx7d"; |
| |
| chosen { |
| stdout-path = &uart6; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x40000000>; |
| }; |
| |
| reg_brcm: regulator-brcm { |
| compatible = "regulator-fixed"; |
| regulator-name = "brcm_reg"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_brcm_reg>; |
| gpio = <&gpio6 13 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| startup-delay-us = <150>; |
| }; |
| |
| wifi_pwrseq: wifi_pwrseq { |
| compatible = "mmc-pwrseq-simple"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wifi>; |
| reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; |
| clock-names = "ext_clock"; |
| }; |
| }; |
| |
| &clks { |
| assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, |
| <&clks IMX7D_CLKO2_ROOT_DIV>; |
| assigned-clock-parents = <&clks IMX7D_CKIL>; |
| assigned-clock-rates = <0>, <32768>; |
| }; |
| |
| &snvs_pwrkey { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; |
| status = "okay"; |
| }; |
| |
| &uart6 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart6>; |
| assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; |
| assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| srp-disable; |
| hnp-disable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
| mmc-pwrseq = <&wifi_pwrseq>; |
| vmmc-supply = <®_brcm>; |
| bus-width = <4>; |
| non-removable; |
| keep-power-in-suspend; |
| cap-power-off-card; |
| status = "okay"; |
| |
| brcmf: bcrmf@1 { |
| reg = <1>; |
| compatible = "brcm,bcm4329-fmac"; |
| }; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| pinctrl-3 = <&pinctrl_usdhc3>; |
| assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| }; |
| |
| &iomuxc { |
| pinctrl_brcm_reg: brcmreggrp { |
| fsl,pins = < |
| /* WIFI_PWR_EN */ |
| MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x14 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 |
| MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 |
| >; |
| }; |
| |
| pinctrl_uart6: uart6grp { |
| fsl,pins = < |
| MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79 |
| MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x59 |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x19 |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5a |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1a |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD2_CMD__SD2_CMD 0x5b |
| MX7D_PAD_SD2_CLK__SD2_CLK 0x1b |
| MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b |
| MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b |
| MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b |
| MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x59 |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x19 |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5a |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x1a |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { |
| fsl,pins = < |
| MX7D_PAD_SD3_CMD__SD3_CMD 0x5b |
| MX7D_PAD_SD3_CLK__SD3_CLK 0x1b |
| MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b |
| MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b |
| MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b |
| MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b |
| MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b |
| MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b |
| MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b |
| MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b |
| MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x74 |
| >; |
| }; |
| |
| pinctrl_wifi: wifigrp { |
| fsl,pins = < |
| /* WiFi Reg On */ |
| MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x00000014 |
| /* WiFi Sleep 32k */ |
| MX7D_PAD_SD1_WP__CCM_CLKO2 0x00000014 |
| >; |
| }; |
| }; |
