| # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Qualcomm Display DPU dt properties for SC7280 |
| |
| maintainers: |
| - Krishna Manikandan <mkrishn@codeaurora.org> |
| |
| description: | |
| Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates |
| sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree |
| bindings of MDSS and DPU are mentioned for SC7280. |
| |
| properties: |
| compatible: |
| const: qcom,sc7280-mdss |
| |
| reg: |
| maxItems: 1 |
| |
| reg-names: |
| const: mdss |
| |
| power-domains: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: Display AHB clock from gcc |
| - description: Display AHB clock from dispcc |
| - description: Display core clock |
| |
| clock-names: |
| items: |
| - const: iface |
| - const: ahb |
| - const: core |
| |
| interrupts: |
| maxItems: 1 |
| |
| interrupt-controller: true |
| |
| "#address-cells": true |
| |
| "#size-cells": true |
| |
| "#interrupt-cells": |
| const: 1 |
| |
| iommus: |
| items: |
| - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 |
| |
| ranges: true |
| |
| interconnects: |
| items: |
| - description: Interconnect path specifying the port ids for data bus |
| |
| interconnect-names: |
| const: mdp0-mem |
| |
| patternProperties: |
| "^display-controller@[0-9a-f]+$": |
| type: object |
| description: Node containing the properties of DPU. |
| |
| properties: |
| compatible: |
| const: qcom,sc7280-dpu |
| |
| reg: |
| items: |
| - description: Address offset and size for mdp register set |
| - description: Address offset and size for vbif register set |
| |
| reg-names: |
| items: |
| - const: mdp |
| - const: vbif |
| |
| clocks: |
| items: |
| - description: Display hf axi clock |
| - description: Display sf axi clock |
| - description: Display ahb clock |
| - description: Display lut clock |
| - description: Display core clock |
| - description: Display vsync clock |
| |
| clock-names: |
| items: |
| - const: bus |
| - const: nrt_bus |
| - const: iface |
| - const: lut |
| - const: core |
| - const: vsync |
| |
| interrupts: |
| maxItems: 1 |
| |
| power-domains: |
| maxItems: 1 |
| |
| operating-points-v2: true |
| |
| ports: |
| $ref: /schemas/graph.yaml#/properties/ports |
| description: | |
| Contains the list of output ports from DPU device. These ports |
| connect to interfaces that are external to the DPU hardware, |
| such as DSI, DP etc. Each output port contains an endpoint that |
| describes how it is connected to an external interface. |
| |
| properties: |
| port@0: |
| $ref: /schemas/graph.yaml#/properties/port |
| description: DPU_INTF1 (DSI) |
| |
| port@1: |
| $ref: /schemas/graph.yaml#/properties/port |
| description: DPU_INTF5 (EDP) |
| |
| required: |
| - port@0 |
| |
| required: |
| - compatible |
| - reg |
| - reg-names |
| - clocks |
| - interrupts |
| - power-domains |
| - operating-points-v2 |
| - ports |
| |
| required: |
| - compatible |
| - reg |
| - reg-names |
| - power-domains |
| - clocks |
| - interrupts |
| - interrupt-controller |
| - iommus |
| - ranges |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/qcom,dispcc-sc7280.h> |
| #include <dt-bindings/clock/qcom,gcc-sc7280.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interconnect/qcom,sc7280.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| |
| display-subsystem@ae00000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,sc7280-mdss"; |
| reg = <0xae00000 0x1000>; |
| reg-names = "mdss"; |
| power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; |
| clocks = <&gcc GCC_DISP_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>; |
| clock-names = "iface", |
| "ahb", |
| "core"; |
| |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; |
| interconnect-names = "mdp0-mem"; |
| |
| iommus = <&apps_smmu 0x900 0x402>; |
| ranges; |
| |
| display-controller@ae01000 { |
| compatible = "qcom,sc7280-dpu"; |
| reg = <0x0ae01000 0x8f000>, |
| <0x0aeb0000 0x2008>; |
| |
| reg-names = "mdp", "vbif"; |
| |
| clocks = <&gcc GCC_DISP_HF_AXI_CLK>, |
| <&gcc GCC_DISP_SF_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>, |
| <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| clock-names = "bus", |
| "nrt_bus", |
| "iface", |
| "lut", |
| "core", |
| "vsync"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <0>; |
| power-domains = <&rpmhpd SC7280_CX>; |
| operating-points-v2 = <&mdp_opp_table>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dpu_intf1_out: endpoint { |
| remote-endpoint = <&dsi0_in>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dpu_intf5_out: endpoint { |
| remote-endpoint = <&edp_in>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| ... |
