| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM |
| */ |
| |
| /dts-v1/; |
| |
| #include "k3-j721e.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/net/ti-dp83867.h> |
| |
| / { |
| compatible = "ti,j721e-sk", "ti,j721e"; |
| model = "Texas Instruments J721E SK"; |
| |
| chosen { |
| stdout-path = "serial2:115200n8"; |
| bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* 4G RAM */ |
| reg = <0x00000000 0x80000000 0x00000000 0x80000000>, |
| <0x00000008 0x80000000 0x00000000 0x80000000>; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| secure_ddr: optee@9e800000 { |
| reg = <0x00 0x9e800000 0x00 0x01800000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa0100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa1100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core0_memory_region: r5f-memory@a2100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa2100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss0_core1_memory_region: r5f-memory@a3100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa3100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core0_memory_region: r5f-memory@a4100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa4100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| main_r5fss1_core1_memory_region: r5f-memory@a5100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa5100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c66_1_dma_memory_region: c66-dma-memory@a6000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c66_0_memory_region: c66-memory@a6100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa6100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c66_0_dma_memory_region: c66-dma-memory@a7000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c66_1_memory_region: c66-memory@a7100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa7100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| c71_0_dma_memory_region: c71-dma-memory@a8000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8000000 0x00 0x100000>; |
| no-map; |
| }; |
| |
| c71_0_memory_region: c71-memory@a8100000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0xa8100000 0x00 0xf00000>; |
| no-map; |
| }; |
| |
| rtos_ipc_memory_region: ipc-memories@aa000000 { |
| reg = <0x00 0xaa000000 0x00 0x01c00000>; |
| alignment = <0x1000>; |
| no-map; |
| }; |
| }; |
| |
| vusb_main: fixedregulator-vusb-main5v0 { |
| /* USB MAIN INPUT 5V DC */ |
| compatible = "regulator-fixed"; |
| regulator-name = "vusb-main5v0"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vsys_3v3: fixedregulator-vsys3v3 { |
| /* Output of LM5141 */ |
| compatible = "regulator-fixed"; |
| regulator-name = "vsys_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| vin-supply = <&vusb_main>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vdd_mmc1: fixedregulator-sd { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&vdd_mmc1_en_pins_default>; |
| regulator-name = "vdd_mmc1"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| enable-active-high; |
| vin-supply = <&vsys_3v3>; |
| gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| vdd_sd_dv_alt: gpio-regulator-tps659411 { |
| compatible = "regulator-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; |
| regulator-name = "tps659411"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| vin-supply = <&vsys_3v3>; |
| gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; |
| states = <1800000 0x0>, |
| <3300000 0x1>; |
| }; |
| |
| dp_pwr_3v3: fixedregulator-dp-prw { |
| compatible = "regulator-fixed"; |
| regulator-name = "dp-pwr"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dp_pwr_en_pins_default>; |
| gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ |
| enable-active-high; |
| }; |
| |
| }; |
| |
| &main_pmx0 { |
| main_mmc1_pins_default: main-mmc1-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ |
| J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ |
| J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ |
| J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ |
| J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ |
| J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ |
| J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ |
| J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ |
| >; |
| }; |
| |
| main_uart0_pins_default: main-uart0-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ |
| J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ |
| J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ |
| J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ |
| >; |
| }; |
| |
| main_i2c0_pins_default: main-i2c0-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ |
| J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ |
| >; |
| }; |
| |
| main_i2c1_pins_default: main-i2c1-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ |
| J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ |
| >; |
| }; |
| |
| main_i2c3_pins_default: main-i2c3-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ |
| J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ |
| >; |
| }; |
| |
| main_usbss0_pins_default: main-usbss0-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ |
| J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ |
| >; |
| }; |
| |
| main_usbss1_pins_default: main-usbss1-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ |
| >; |
| }; |
| |
| dp0_pins_default: dp0-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ |
| >; |
| }; |
| |
| dp_pwr_en_pins_default: dp-pwr-en-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ |
| >; |
| }; |
| |
| dss_vout0_pins_default: dss-vout0-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ |
| J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ |
| J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ |
| J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ |
| J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ |
| J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ |
| J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ |
| J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ |
| J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ |
| J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ |
| J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ |
| J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ |
| J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ |
| J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ |
| J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ |
| J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ |
| J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ |
| J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ |
| J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ |
| J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ |
| J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ |
| J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ |
| J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ |
| J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ |
| J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ |
| J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ |
| J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ |
| J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ |
| >; |
| }; |
| |
| /* Reset for M.2 E Key slot on PCIe0 */ |
| ekey_reset_pins_default: ekey-reset-pns-pins-default { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ |
| >; |
| }; |
| }; |
| |
| &wkup_pmx0 { |
| mcu_cpsw_pins_default: mcu-cpsw-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ |
| J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ |
| J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ |
| J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ |
| J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ |
| J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ |
| J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ |
| J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ |
| J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ |
| J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ |
| J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ |
| J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ |
| >; |
| }; |
| |
| mcu_mdio_pins_default: mcu-mdio1-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ |
| J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ |
| >; |
| }; |
| |
| mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ |
| J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ |
| J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ |
| J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ |
| J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ |
| J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ |
| J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ |
| J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ |
| J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ |
| J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ |
| J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ |
| >; |
| }; |
| |
| vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ |
| >; |
| }; |
| |
| vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ |
| >; |
| }; |
| |
| wkup_i2c0_pins_default: wkup-i2c0-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ |
| J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ |
| >; |
| }; |
| |
| /* Reset for M.2 M Key slot on PCIe1 */ |
| mkey_reset_pins_default: mkey-reset-pns-pins-default { |
| pinctrl-single,pins = < |
| J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ |
| >; |
| }; |
| }; |
| |
| &wkup_uart0 { |
| /* Wakeup UART is used by System firmware */ |
| status = "reserved"; |
| }; |
| |
| &main_uart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_uart0_pins_default>; |
| /* Shared with ATF on this platform */ |
| power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; |
| }; |
| |
| &main_uart2 { |
| /* Brought out on RPi header */ |
| status = "disabled"; |
| }; |
| |
| &main_uart3 { |
| /* UART not brought out */ |
| status = "disabled"; |
| }; |
| |
| &main_uart5 { |
| /* UART not brought out */ |
| status = "disabled"; |
| }; |
| |
| &main_uart6 { |
| /* UART not brought out */ |
| status = "disabled"; |
| }; |
| |
| &main_uart7 { |
| /* UART not brought out */ |
| status = "disabled"; |
| }; |
| |
| &main_uart8 { |
| /* UART not brought out */ |
| status = "disabled"; |
| }; |
| |
| &main_uart9 { |
| /* Brought out on M.2 E Key */ |
| status = "disabled"; |
| }; |
| |
| &main_sdhci0 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &main_sdhci1 { |
| /* SD Card */ |
| vmmc-supply = <&vdd_mmc1>; |
| vqmmc-supply = <&vdd_sd_dv_alt>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_mmc1_pins_default>; |
| ti,driver-strength-ohm = <50>; |
| disable-wp; |
| }; |
| |
| &main_sdhci2 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &ospi0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0x0>; |
| spi-tx-bus-width = <8>; |
| spi-rx-bus-width = <8>; |
| spi-max-frequency = <25000000>; |
| cdns,tshsl-ns = <60>; |
| cdns,tsd2d-ns = <60>; |
| cdns,tchsh-ns = <60>; |
| cdns,tslch-ns = <60>; |
| cdns,read-delay = <4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| }; |
| |
| &ospi1 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &main_i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c0_pins_default>; |
| clock-frequency = <400000>; |
| |
| i2c-mux@71 { |
| compatible = "nxp,pca9543"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x71>; |
| |
| /* PCIe1 M.2 M Key I2C */ |
| i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| }; |
| |
| /* PCIe0 M.2 E Key I2C */ |
| i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &main_i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c1_pins_default>; |
| /* i2c1 is used for DVI DDC, so we need to use 100kHz */ |
| clock-frequency = <100000>; |
| }; |
| |
| &main_i2c2 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &main_i2c3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_i2c3_pins_default>; |
| clock-frequency = <400000>; |
| |
| i2c-mux@70 { |
| compatible = "nxp,pca9543"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70>; |
| |
| /* CSI0 I2C */ |
| i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| }; |
| |
| /* CSI1 I2C */ |
| i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &main_i2c4 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &main_i2c5 { |
| /* Brought out on RPi Header */ |
| status = "disabled"; |
| }; |
| |
| &main_i2c6 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &main_gpio2 { |
| status = "disabled"; |
| }; |
| |
| &main_gpio3 { |
| status = "disabled"; |
| }; |
| |
| &main_gpio4 { |
| status = "disabled"; |
| }; |
| |
| &main_gpio5 { |
| status = "disabled"; |
| }; |
| |
| &main_gpio6 { |
| status = "disabled"; |
| }; |
| |
| &main_gpio7 { |
| status = "disabled"; |
| }; |
| |
| &wkup_gpio1 { |
| status = "disabled"; |
| }; |
| |
| &main_r5fss0_core0{ |
| firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; |
| }; |
| |
| &usb_serdes_mux { |
| idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ |
| }; |
| |
| &serdes_ln_ctrl { |
| idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, |
| <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, |
| <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, |
| <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, |
| <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, |
| <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; |
| }; |
| |
| &serdes_wiz3 { |
| typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; |
| typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ |
| }; |
| |
| &serdes3 { |
| serdes3_usb_link: phy@0 { |
| reg = <0>; |
| cdns,num-lanes = <2>; |
| #phy-cells = <0>; |
| cdns,phy-type = <PHY_TYPE_USB3>; |
| resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; |
| }; |
| }; |
| |
| &usbss0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_usbss0_pins_default>; |
| ti,vbus-divider; |
| }; |
| |
| &usb0 { |
| dr_mode = "otg"; |
| maximum-speed = "super-speed"; |
| phys = <&serdes3_usb_link>; |
| phy-names = "cdns3,usb3-phy"; |
| }; |
| |
| &serdes2 { |
| serdes2_usb_link: phy@1 { |
| reg = <1>; |
| cdns,num-lanes = <1>; |
| #phy-cells = <0>; |
| cdns,phy-type = <PHY_TYPE_USB3>; |
| resets = <&serdes_wiz2 2>; |
| }; |
| }; |
| |
| &usbss1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&main_usbss1_pins_default>; |
| ti,vbus-divider; |
| }; |
| |
| &usb1 { |
| dr_mode = "host"; |
| maximum-speed = "super-speed"; |
| phys = <&serdes2_usb_link>; |
| phy-names = "cdns3,usb3-phy"; |
| }; |
| |
| &tscadc0 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &tscadc1 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcu_cpsw { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; |
| }; |
| |
| &davinci_mdio { |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| }; |
| }; |
| |
| &cpsw_port1 { |
| phy-mode = "rgmii-rxid"; |
| phy-handle = <&phy0>; |
| }; |
| |
| &dss { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&dss_vout0_pins_default>; |
| |
| assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ |
| <&k3_clks 152 4>, /* VP 2 pixel clock */ |
| <&k3_clks 152 9>, /* VP 3 pixel clock */ |
| <&k3_clks 152 13>; /* VP 4 pixel clock */ |
| assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ |
| <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ |
| <&k3_clks 152 11>, /* PLL18_HSDIV0 */ |
| <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ |
| }; |
| |
| &mcasp0 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp1 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp2 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp3 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp4 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp5 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp6 { |
| /* Brought out on RPi header */ |
| status = "disabled"; |
| }; |
| |
| &mcasp7 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp8 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp9 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp10 { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &mcasp11 { |
| /* Brought out on M.2 E Key */ |
| status = "disabled"; |
| }; |
| |
| &serdes0 { |
| serdes0_pcie_link: phy@0 { |
| reg = <0>; |
| cdns,num-lanes = <1>; |
| #phy-cells = <0>; |
| cdns,phy-type = <PHY_TYPE_PCIE>; |
| resets = <&serdes_wiz0 1>; |
| }; |
| }; |
| |
| &serdes1 { |
| serdes1_pcie_link: phy@0 { |
| reg = <0>; |
| cdns,num-lanes = <2>; |
| #phy-cells = <0>; |
| cdns,phy-type = <PHY_TYPE_PCIE>; |
| resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; |
| }; |
| }; |
| |
| &pcie0_rc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ekey_reset_pins_default>; |
| reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; |
| |
| phys = <&serdes0_pcie_link>; |
| phy-names = "pcie-phy"; |
| num-lanes = <1>; |
| }; |
| |
| &pcie1_rc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mkey_reset_pins_default>; |
| reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; |
| |
| phys = <&serdes1_pcie_link>; |
| phy-names = "pcie-phy"; |
| num-lanes = <2>; |
| }; |
| |
| &pcie2_rc { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &pcie0_ep { |
| status = "disabled"; |
| phys = <&serdes0_pcie_link>; |
| phy-names = "pcie-phy"; |
| num-lanes = <1>; |
| }; |
| |
| &pcie1_ep { |
| status = "disabled"; |
| phys = <&serdes1_pcie_link>; |
| phy-names = "pcie-phy"; |
| num-lanes = <2>; |
| }; |
| |
| &pcie2_ep { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &pcie3_rc { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &pcie3_ep { |
| /* Unused */ |
| status = "disabled"; |
| }; |
| |
| &dss { |
| status = "disabled"; |
| }; |
| |
| &icssg0_mdio { |
| status = "disabled"; |
| }; |
| |
| &icssg1_mdio { |
| status = "disabled"; |
| }; |
| |
| &ufs_wrapper { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster0 { |
| interrupts = <436>; |
| |
| mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster1 { |
| interrupts = <432>; |
| |
| mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster2 { |
| interrupts = <428>; |
| |
| mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster3 { |
| interrupts = <424>; |
| |
| mbox_c66_0: mbox-c66-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| |
| mbox_c66_1: mbox-c66-1 { |
| ti,mbox-rx = <2 0 0>; |
| ti,mbox-tx = <3 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster4 { |
| interrupts = <420>; |
| |
| mbox_c71_0: mbox-c71-0 { |
| ti,mbox-rx = <0 0 0>; |
| ti,mbox-tx = <1 0 0>; |
| }; |
| }; |
| |
| &mailbox0_cluster5 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster6 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster7 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster8 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster9 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster10 { |
| status = "disabled"; |
| }; |
| |
| &mailbox0_cluster11 { |
| status = "disabled"; |
| }; |
| |
| &mcu_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; |
| memory-region = <&mcu_r5fss0_core0_dma_memory_region>, |
| <&mcu_r5fss0_core0_memory_region>; |
| }; |
| |
| &mcu_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; |
| memory-region = <&mcu_r5fss0_core1_dma_memory_region>, |
| <&mcu_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss0_core0 { |
| mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; |
| memory-region = <&main_r5fss0_core0_dma_memory_region>, |
| <&main_r5fss0_core0_memory_region>; |
| }; |
| |
| &main_r5fss0_core1 { |
| mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; |
| memory-region = <&main_r5fss0_core1_dma_memory_region>, |
| <&main_r5fss0_core1_memory_region>; |
| }; |
| |
| &main_r5fss1_core0 { |
| mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; |
| memory-region = <&main_r5fss1_core0_dma_memory_region>, |
| <&main_r5fss1_core0_memory_region>; |
| }; |
| |
| &main_r5fss1_core1 { |
| mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; |
| memory-region = <&main_r5fss1_core1_dma_memory_region>, |
| <&main_r5fss1_core1_memory_region>; |
| }; |
| |
| &c66_0 { |
| mboxes = <&mailbox0_cluster3 &mbox_c66_0>; |
| memory-region = <&c66_0_dma_memory_region>, |
| <&c66_0_memory_region>; |
| }; |
| |
| &c66_1 { |
| mboxes = <&mailbox0_cluster3 &mbox_c66_1>; |
| memory-region = <&c66_1_dma_memory_region>, |
| <&c66_1_memory_region>; |
| }; |
| |
| &c71_0 { |
| mboxes = <&mailbox0_cluster4 &mbox_c71_0>; |
| memory-region = <&c71_0_dma_memory_region>, |
| <&c71_0_memory_region>; |
| }; |
