Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)

ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
with a shared L3 memory system, control logic and external interfaces to
form a multicore cluster. The PMU enables to gather various statistics on
the operations of the DSU. The PMU provides independent 32bit counters that
can count any of the supported events, along with a 64bit cycle counter.
The PMU is accessed via CPU system registers and has no MMIO component.

** DSU PMU required properties:

- compatible	: should be one of :

		"arm,dsu-pmu"

- interrupts	: Exactly 1 SPI must be listed.

- cpus		: List of phandles for the CPUs connected to this DSU instance.


** Example:

dsu-pmu-0 {
	compatible = "arm,dsu-pmu";
	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
	cpus = <&cpu_0>, <&cpu_1>;
};