| Atmel system registers |
| |
| Chipid required properties: |
| - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" |
| - reg : Should contain registers location and length |
| |
| PIT Timer required properties: |
| - compatible: Should be "atmel,at91sam9260-pit" |
| - reg: Should contain registers location and length |
| - interrupts: Should contain interrupt for the PIT which is the IRQ line |
| shared across all System Controller members. |
| |
| PIT64B Timer required properties: |
| - compatible: Should be "microchip,sam9x60-pit64b" |
| - reg: Should contain registers location and length |
| - interrupts: Should contain interrupt for PIT64B timer |
| - clocks: Should contain the available clock sources for PIT64B timer. |
| |
| System Timer (ST) required properties: |
| - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" |
| - reg: Should contain registers location and length |
| - interrupts: Should contain interrupt for the ST which is the IRQ line |
| shared across all System Controller members. |
| - clocks: phandle to input clock. |
| Its subnodes can be: |
| - watchdog: compatible should be "atmel,at91rm9200-wdt" |
| |
| RSTC Reset Controller required properties: |
| - compatible: Should be "atmel,<chip>-rstc". |
| <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" |
| it also can be "microchip,sam9x60-rstc" |
| - reg: Should contain registers location and length |
| - clocks: phandle to input clock. |
| |
| Example: |
| |
| rstc@fffffd00 { |
| compatible = "atmel,at91sam9260-rstc"; |
| reg = <0xfffffd00 0x10>; |
| clocks = <&clk32k>; |
| }; |
| |
| RAMC SDRAM/DDR Controller required properties: |
| - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" |
| "atmel,at91sam9260-sdramc", |
| "atmel,at91sam9g45-ddramc", |
| "atmel,sama5d3-ddramc", |
| "microchip,sam9x60-ddramc", |
| "microchip,sama7g5-uddrc" |
| - reg: Should contain registers location and length |
| |
| Examples: |
| |
| ramc0: ramc@ffffe800 { |
| compatible = "atmel,at91sam9g45-ddramc"; |
| reg = <0xffffe800 0x200>; |
| }; |
| |
| RAMC PHY Controller required properties: |
| - compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" |
| - reg: Should contain registers location and length |
| |
| Example: |
| |
| ddr3phy: ddr3phy@e3804000 { |
| compatible = "microchip,sama7g5-ddr3phy", "syscon"; |
| reg = <0xe3804000 0x1000>; |
| }; |
| |
| SHDWC Shutdown Controller |
| |
| required properties: |
| - compatible: Should be "atmel,<chip>-shdwc". |
| <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". |
| - reg: Should contain registers location and length |
| - clocks: phandle to input clock. |
| |
| optional properties: |
| - atmel,wakeup-mode: String, operation mode of the wakeup mode. |
| Supported values are: "none", "high", "low", "any". |
| - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). |
| |
| optional at91sam9260 properties: |
| - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
| |
| optional at91sam9rl properties: |
| - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. |
| - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
| |
| optional at91sam9x5 properties: |
| - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. |
| |
| Example: |
| |
| shdwc@fffffd10 { |
| compatible = "atmel,at91sam9260-shdwc"; |
| reg = <0xfffffd10 0x10>; |
| clocks = <&clk32k>; |
| }; |
| |
| SHDWC SAMA5D2-Compatible Shutdown Controller |
| |
| 1) shdwc node |
| |
| required properties: |
| - compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or |
| "microchip,sama7g5-shdwc" |
| - reg: should contain registers location and length |
| - clocks: phandle to input clock. |
| - #address-cells: should be one. The cell is the wake-up input index. |
| - #size-cells: should be zero. |
| |
| optional properties: |
| |
| - debounce-delay-us: minimum wake-up inputs debouncer period in |
| microseconds. It's usually a board-related property. |
| - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. |
| |
| optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: |
| - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. |
| |
| The node contains child nodes for each wake-up input that the platform uses. |
| |
| 2) input nodes |
| |
| Wake-up input nodes are usually described in the "board" part of the Device |
| Tree. Note also that input 0 is linked to the wake-up pin and is frequently |
| used. |
| |
| Required properties: |
| - reg: should contain the wake-up input index [0 - 15]. |
| |
| Optional properties: |
| - atmel,wakeup-active-high: boolean, the corresponding wake-up input described |
| by the child, forces the wake-up of the core power supply on a high level. |
| The default is to be active low. |
| |
| Example: |
| |
| On the SoC side: |
| shdwc@f8048010 { |
| compatible = "atmel,sama5d2-shdwc"; |
| reg = <0xf8048010 0x10>; |
| clocks = <&clk32k>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| atmel,wakeup-rtc-timer; |
| }; |
| |
| On the board side: |
| shdwc@f8048010 { |
| debounce-delay-us = <976>; |
| |
| input@0 { |
| reg = <0>; |
| }; |
| |
| input@1 { |
| reg = <1>; |
| atmel,wakeup-active-high; |
| }; |
| }; |
| |
| Special Function Registers (SFR) |
| |
| Special Function Registers (SFR) manage specific aspects of the integrated |
| memory, bridge implementations, processor and other functionality not controlled |
| elsewhere. |
| |
| required properties: |
| - compatible: Should be "atmel,<chip>-sfr", "syscon" or |
| "atmel,<chip>-sfrbu", "syscon" |
| <chip> can be "sama5d3", "sama5d4" or "sama5d2". |
| It also can be "microchip,sam9x60-sfr", "syscon". |
| - reg: Should contain registers location and length |
| |
| sfr@f0038000 { |
| compatible = "atmel,sama5d3-sfr", "syscon"; |
| reg = <0xf0038000 0x60>; |
| }; |
| |
| Security Module (SECUMOD) |
| |
| The Security Module macrocell provides all necessary secure functions to avoid |
| voltage, temperature, frequency and mechanical attacks on the chip. It also |
| embeds secure memories that can be scrambled. |
| |
| The Security Module also offers the PIOBU pins which can be used as GPIO pins. |
| Note that they maintain their voltage during Backup/Self-refresh. |
| |
| required properties: |
| - compatible: Should be "atmel,<chip>-secumod", "syscon". |
| <chip> can be "sama5d2". |
| - reg: Should contain registers location and length |
| - gpio-controller: Marks the port as GPIO controller. |
| - #gpio-cells: There are 2. The pin number is the |
| first, the second represents additional |
| parameters such as GPIO_ACTIVE_HIGH/LOW. |
| |
| |
| secumod@fc040000 { |
| compatible = "atmel,sama5d2-secumod", "syscon"; |
| reg = <0xfc040000 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |