| * Hisilicon Hi3660 Clock Controller |
| |
| The Hi3660 clock controller generates and supplies clock to various |
| controllers within the Hi3660 SoC. |
| |
| Required Properties: |
| |
| - compatible: the compatible should be one of the following strings to |
| indicate the clock controller functionality. |
| |
| - "hisilicon,hi3660-crgctrl" |
| - "hisilicon,hi3660-pctrl" |
| - "hisilicon,hi3660-pmuctrl" |
| - "hisilicon,hi3660-sctrl" |
| - "hisilicon,hi3660-iomcu" |
| - "hisilicon,hi3660-stub-clk" |
| |
| - reg: physical base address of the controller and length of memory mapped |
| region. |
| |
| - #clock-cells: should be 1. |
| |
| Optional Properties: |
| |
| - mboxes: Phandle to the mailbox for sending message to MCU. |
| (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info) |
| |
| Each clock is assigned an identifier and client nodes use this identifier |
| to specify the clock which they consume. |
| |
| All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>. |
| |
| Examples: |
| crg_ctrl: clock-controller@fff35000 { |
| compatible = "hisilicon,hi3660-crgctrl", "syscon"; |
| reg = <0x0 0xfff35000 0x0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| uart0: serial@fdf02000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x0 0xfdf02000 0x0 0x1000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, |
| <&crg_ctrl HI3660_PCLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| }; |