| // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) |
| // |
| // This file is provided under a dual BSD/GPLv2 license. When using or |
| // redistributing this file, you may do so under either license. |
| // |
| // Copyright(c) 2018 Intel Corporation. All rights reserved. |
| // |
| // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> |
| // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> |
| // Rander Wang <rander.wang@intel.com> |
| // Keyon Jie <yang.jie@linux.intel.com> |
| // |
| |
| /* |
| * Hardware interface for audio DSP on Apollolake and GeminiLake |
| */ |
| |
| #include "../sof-priv.h" |
| #include "hda.h" |
| |
| static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = { |
| {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
| {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
| {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
| }; |
| |
| /* apollolake ops */ |
| const struct snd_sof_dsp_ops sof_apl_ops = { |
| /* probe and remove */ |
| .probe = hda_dsp_probe, |
| .remove = hda_dsp_remove, |
| |
| /* Register IO */ |
| .write = sof_io_write, |
| .read = sof_io_read, |
| .write64 = sof_io_write64, |
| .read64 = sof_io_read64, |
| |
| /* Block IO */ |
| .block_read = sof_block_read, |
| .block_write = sof_block_write, |
| |
| /* doorbell */ |
| .irq_handler = hda_dsp_ipc_irq_handler, |
| .irq_thread = hda_dsp_ipc_irq_thread, |
| |
| /* ipc */ |
| .send_msg = hda_dsp_ipc_send_msg, |
| .fw_ready = sof_fw_ready, |
| .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset, |
| .get_window_offset = hda_dsp_ipc_get_window_offset, |
| |
| .ipc_msg_data = hda_ipc_msg_data, |
| .ipc_pcm_params = hda_ipc_pcm_params, |
| |
| /* debug */ |
| .debug_map = apl_dsp_debugfs, |
| .debug_map_count = ARRAY_SIZE(apl_dsp_debugfs), |
| .dbg_dump = hda_dsp_dump, |
| .ipc_dump = hda_ipc_dump, |
| |
| /* stream callbacks */ |
| .pcm_open = hda_dsp_pcm_open, |
| .pcm_close = hda_dsp_pcm_close, |
| .pcm_hw_params = hda_dsp_pcm_hw_params, |
| .pcm_hw_free = hda_dsp_stream_hw_free, |
| .pcm_trigger = hda_dsp_pcm_trigger, |
| .pcm_pointer = hda_dsp_pcm_pointer, |
| |
| /* firmware loading */ |
| .load_firmware = snd_sof_load_firmware_raw, |
| |
| /* firmware run */ |
| .run = hda_dsp_cl_boot_firmware, |
| |
| /* pre/post fw run */ |
| .pre_fw_run = hda_dsp_pre_fw_run, |
| .post_fw_run = hda_dsp_post_fw_run, |
| |
| /* dsp core power up/down */ |
| .core_power_up = hda_dsp_enable_core, |
| .core_power_down = hda_dsp_core_reset_power_down, |
| |
| /* trace callback */ |
| .trace_init = hda_dsp_trace_init, |
| .trace_release = hda_dsp_trace_release, |
| .trace_trigger = hda_dsp_trace_trigger, |
| |
| /* DAI drivers */ |
| .drv = skl_dai, |
| .num_drv = SOF_SKL_NUM_DAIS, |
| |
| /* PM */ |
| .suspend = hda_dsp_suspend, |
| .resume = hda_dsp_resume, |
| .runtime_suspend = hda_dsp_runtime_suspend, |
| .runtime_resume = hda_dsp_runtime_resume, |
| .runtime_idle = hda_dsp_runtime_idle, |
| .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume, |
| .set_power_state = hda_dsp_set_power_state, |
| |
| /* ALSA HW info flags */ |
| .hw_info = SNDRV_PCM_INFO_MMAP | |
| SNDRV_PCM_INFO_MMAP_VALID | |
| SNDRV_PCM_INFO_INTERLEAVED | |
| SNDRV_PCM_INFO_PAUSE | |
| SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, |
| }; |
| EXPORT_SYMBOL(sof_apl_ops); |
| |
| const struct sof_intel_dsp_desc apl_chip_info = { |
| /* Apollolake */ |
| .cores_num = 2, |
| .init_core_mask = 1, |
| .cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1), |
| .ipc_req = HDA_DSP_REG_HIPCI, |
| .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY, |
| .ipc_ack = HDA_DSP_REG_HIPCIE, |
| .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE, |
| .ipc_ctl = HDA_DSP_REG_HIPCCTL, |
| .rom_init_timeout = 150, |
| .ssp_count = APL_SSP_COUNT, |
| .ssp_base_offset = APL_SSP_BASE_OFFSET, |
| }; |
| EXPORT_SYMBOL(apl_chip_info); |