| /* SPDX-License-Identifier: GPL-2.0-only */ |
| * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
| #ifndef __DT_BINDINGS_CLOCK_IMX1_H |
| #define __DT_BINDINGS_CLOCK_IMX1_H |
| #define IMX1_CLK_CLK16M_EXT 2 |
| #define IMX1_CLK_CLK16M 3 |
| #define IMX1_CLK_CLK32_PREMULT 4 |
| #define IMX1_CLK_MPLL_GATE 7 |
| #define IMX1_CLK_SPLL_GATE 9 |
| #define IMX1_CLK_CLK48M 13 |
| #define IMX1_CLK_UART3_GATE 18 |
| #define IMX1_CLK_SSI2_GATE 19 |
| #define IMX1_CLK_BROM_GATE 20 |
| #define IMX1_CLK_DMA_GATE 21 |
| #define IMX1_CLK_CSI_GATE 22 |
| #define IMX1_CLK_MMA_GATE 23 |
| #define IMX1_CLK_USBD_GATE 24 |