Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8450 Display DPU

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    const: qcom,sm8450-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display hf axi
      - description: Display sf axi
      - description: Display ahb
      - description: Display lut
      - description: Display core
      - description: Display vsync

  clock-names:
    items:
      - const: bus
      - const: nrt_bus
      - const: iface
      - const: lut
      - const: core
      - const: vsync

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sm8450.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    display-controller@ae01000 {
        compatible = "qcom,sm8450-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;
        reg-names = "mdp", "vbif";

        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                <&gcc GCC_DISP_SF_AXI_CLK>,
                <&dispcc DISP_CC_MDSS_AHB_CLK>,
                <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                <&dispcc DISP_CC_MDSS_MDP_CLK>,
                <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "bus",
                      "nrt_bus",
                      "iface",
                      "lut",
                      "core",
                      "vsync";

        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        assigned-clock-rates = <19200000>;

        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmhpd RPMHPD_MMCX>;

        interrupt-parent = <&mdss>;
        interrupts = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                dpu_intf1_out: endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@1 {
                reg = <1>;
                dpu_intf2_out: endpoint {
                    remote-endpoint = <&dsi1_in>;
                };
            };
        };

        mdp_opp_table: opp-table {
            compatible = "operating-points-v2";

            opp-172000000{
                opp-hz = /bits/ 64 <172000000>;
                required-opps = <&rpmhpd_opp_low_svs_d1>;
            };

            opp-200000000 {
                opp-hz = /bits/ 64 <200000000>;
                required-opps = <&rpmhpd_opp_low_svs>;
            };

            opp-325000000 {
                opp-hz = /bits/ 64 <325000000>;
                required-opps = <&rpmhpd_opp_svs>;
            };

            opp-375000000 {
                opp-hz = /bits/ 64 <375000000>;
                required-opps = <&rpmhpd_opp_svs_l1>;
            };

            opp-500000000 {
                opp-hz = /bits/ 64 <500000000>;
                required-opps = <&rpmhpd_opp_nom>;
            };
        };
    };
...