Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Read Direct Memory Access

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
  It contains one line buffer to store the sufficient pixel data, and
  must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt8183-mdp3-rdma
          - mediatek,mt8195-mdp3-rdma
          - mediatek,mt8195-vdo1-rdma
      - items:
          - const: mediatek,mt8188-vdo1-rdma
          - const: mediatek,mt8195-vdo1-rdma

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  mediatek,scp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the System Control Processor (SCP) used for initializing
      and stopping the MDP3, for sending frame data locations to the MDP3's
      VPU and to install Inter-Processor Interrupt handlers to control
      processing states.

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: RDMA clock
      - description: RSZ clock
    minItems: 1

  iommus:
    maxItems: 1

  mboxes:
    items:
      - description: used for 1st data pipe from RDMA
      - description: used for 2nd data pipe from RDMA
      - description: used for 3rd data pipe from RDMA
      - description: used for 4th data pipe from RDMA
      - description: used for the data pipe from SPLIT
    minItems: 1

  interrupts:
    maxItems: 1

  '#dma-cells':
    const: 1

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - power-domains
  - clocks
  - iommus
  - '#dma-cells'

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8183-mdp3-rdma

    then:
      properties:
        clocks:
          minItems: 2

        mboxes:
          minItems: 2

      required:
        - mboxes
        - mediatek,gce-events

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8195-mdp3-rdma

    then:
      properties:
        clocks:
          maxItems: 1

        mboxes:
          minItems: 5

      required:
        - mediatek,gce-events

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8195-vdo1-rdma

    then:
      properties:
        clocks:
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/memory/mt8183-larb-port.h>

    dma-controller@14001000 {
        compatible = "mediatek,mt8183-mdp3-rdma";
        reg = <0x14001000 0x1000>;
        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
        mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
                              <CMDQ_EVENT_MDP_RDMA0_EOF>;
        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
        clocks = <&mmsys CLK_MM_MDP_RDMA0>,
                 <&mmsys CLK_MM_MDP_RSZ1>;
        iommus = <&iommu>;
        mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
                 <&gce 21 CMDQ_THR_PRIO_LOWEST>;
        #dma-cells = <1>;
    };