| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (C) 2023 PHYTEC Messtechnik GmbH |
| * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> |
| * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> |
| * |
| * Product homepage: |
| * phyBOARD-Segin carrier board is reused for the i.MX93 design. |
| * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ |
| */ |
| /dts-v1/; |
| |
| #include "imx93-phycore-som.dtsi" |
| |
| /{ |
| model = "PHYTEC phyBOARD-Segin-i.MX93"; |
| compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", |
| "fsl,imx93"; |
| |
| chosen { |
| stdout-path = &lpuart1; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| enable-active-high; |
| gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "VCC_SD"; |
| }; |
| }; |
| |
| /* Console */ |
| &lpuart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| /* eMMC */ |
| &usdhc1 { |
| no-1-8-v; |
| }; |
| |
| /* SD-Card */ |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; |
| bus-width = <4>; |
| cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; |
| no-mmc; |
| no-sdio; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX93_PAD_UART1_RXD__LPUART1_RX 0x31e |
| MX93_PAD_UART1_TXD__LPUART1_TX 0x30e |
| >; |
| }; |
| |
| pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { |
| fsl,pins = < |
| MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e |
| >; |
| }; |
| |
| pinctrl_usdhc2_cd: usdhc2cdgrp { |
| fsl,pins = < |
| MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e |
| >; |
| }; |
| |
| pinctrl_usdhc2_default: usdhc2grp { |
| fsl,pins = < |
| MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e |
| MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e |
| MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e |
| MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e |
| MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e |
| MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e |
| MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp { |
| fsl,pins = < |
| MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e |
| MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e |
| MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e |
| MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e |
| MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e |
| MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e |
| MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp { |
| fsl,pins = < |
| MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e |
| MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e |
| MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e |
| MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e |
| MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e |
| MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e |
| MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e |
| >; |
| }; |
| }; |
