| [ |
| { |
| "BriefDescription": "Transaction count", |
| "MetricName": "transaction", |
| "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" |
| }, |
| { |
| "BriefDescription": "Cycles per Instruction", |
| "MetricName": "cpi", |
| "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" |
| }, |
| { |
| "BriefDescription": "Problem State Instruction Ratio", |
| "MetricName": "prbstate", |
| "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" |
| }, |
| { |
| "BriefDescription": "Level One Miss per 100 Instructions", |
| "MetricName": "l1mp", |
| "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" |
| }, |
| { |
| "BriefDescription": "Percentage sourced from Level 2 cache", |
| "MetricName": "l2p", |
| "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" |
| }, |
| { |
| "BriefDescription": "Percentage sourced from Level 3 on same chip cache", |
| "MetricName": "l3p", |
| "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" |
| }, |
| { |
| "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", |
| "MetricName": "l4lp", |
| "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" |
| }, |
| { |
| "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", |
| "MetricName": "l4rp", |
| "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" |
| }, |
| { |
| "BriefDescription": "Percentage sourced from memory", |
| "MetricName": "memp", |
| "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" |
| }, |
| { |
| "BriefDescription": "Cycles per Instructions from Finite cache/memory", |
| "MetricName": "finite_cpi", |
| "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" |
| }, |
| { |
| "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", |
| "MetricName": "est_cpi", |
| "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" |
| }, |
| { |
| "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", |
| "MetricName": "scpl1m", |
| "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" |
| }, |
| { |
| "BriefDescription": "Estimated TLB CPU percentage of Total CPU", |
| "MetricName": "tlb_percent", |
| "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" |
| }, |
| { |
| "BriefDescription": "Estimated Cycles per TLB Miss", |
| "MetricName": "tlb_miss", |
| "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" |
| } |
| ] |
