[ | |
{ | |
"ArchStdEvent": "L1I_CACHE_REFILL" | |
}, | |
{ | |
"ArchStdEvent": "L1I_TLB_REFILL" | |
}, | |
{ | |
"ArchStdEvent": "L1D_CACHE_REFILL" | |
}, | |
{ | |
"ArchStdEvent": "L1D_CACHE" | |
}, | |
{ | |
"ArchStdEvent": "L1D_TLB_REFILL" | |
}, | |
{ | |
"ArchStdEvent": "L1I_CACHE" | |
}, | |
{ | |
"ArchStdEvent": "L1D_CACHE_WB" | |
}, | |
{ | |
"ArchStdEvent": "L2D_CACHE" | |
}, | |
{ | |
"ArchStdEvent": "L2D_CACHE_REFILL" | |
}, | |
{ | |
"ArchStdEvent": "L2D_CACHE_WB" | |
} | |
] |