| [ |
| { |
| "ArchStdEvent": "L1I_CACHE_REFILL", |
| "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." |
| }, |
| { |
| "ArchStdEvent": "L1I_CACHE", |
| "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." |
| }, |
| { |
| "ArchStdEvent": "L1I_CACHE_LMISS", |
| "PublicDescription": "Counts cache line refills into the level 1 instruction cache, that incurred additional latency." |
| } |
| ] |
