| // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB |
| /* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ |
| |
| #include "dr_ste_v1.h" |
| |
| enum { |
| DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0 = 0x00, |
| DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1 = 0x01, |
| DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2 = 0x02, |
| DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08, |
| DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09, |
| DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e, |
| DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0 = 0x18, |
| DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1 = 0x19, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_1 = 0x41, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_0 = 0x44, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_1 = 0x45, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_2 = 0x46, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_3 = 0x47, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_0 = 0x4c, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_1 = 0x4d, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_2 = 0x4e, |
| DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_3 = 0x4f, |
| DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_0 = 0x5e, |
| DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_1 = 0x5f, |
| DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_0 = 0x6f, |
| DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_1 = 0x70, |
| DR_STE_V2_ACTION_MDFY_FLD_METADATA_2_CQE = 0x7b, |
| DR_STE_V2_ACTION_MDFY_FLD_GNRL_PURPOSE = 0x7c, |
| DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_0 = 0x90, |
| DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_1 = 0x91, |
| DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_0 = 0x92, |
| DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_1 = 0x93, |
| DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_0 = 0x94, |
| DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_1 = 0x95, |
| }; |
| |
| static const struct mlx5dr_ste_action_modify_field dr_ste_v2_action_modify_field_arr[] = { |
| [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1, .start = 16, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1, .start = 0, .end = 15, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1, .start = 16, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 18, .end = 23, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1, .start = 16, .end = 24, |
| .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31, |
| .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15, |
| .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31, |
| .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15, |
| .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_0, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_1, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_2, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_SRC_OUT_3, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_0, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_1, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_2, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV6_DST_OUT_3, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_1, .start = 0, .end = 31, |
| .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_GNRL_PURPOSE, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_METADATA_2_CQE, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_0, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_0_1, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_0, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_1_1, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_0, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_REGISTER_2_1, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_0, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_TCP_MISC_1, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2, .start = 0, .end = 15, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_EMD_31_0] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_1, .start = 0, .end = 31, |
| }, |
| [MLX5_ACTION_IN_FIELD_OUT_EMD_47_32] = { |
| .hw_field = DR_STE_V2_ACTION_MDFY_FLD_CFG_HDR_0_0, .start = 0, .end = 15, |
| }, |
| }; |
| |
| static struct mlx5dr_ste_ctx ste_ctx_v2 = { |
| /* Builders */ |
| .build_eth_l2_src_dst_init = &dr_ste_v1_build_eth_l2_src_dst_init, |
| .build_eth_l3_ipv6_src_init = &dr_ste_v1_build_eth_l3_ipv6_src_init, |
| .build_eth_l3_ipv6_dst_init = &dr_ste_v1_build_eth_l3_ipv6_dst_init, |
| .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init, |
| .build_eth_l2_src_init = &dr_ste_v1_build_eth_l2_src_init, |
| .build_eth_l2_dst_init = &dr_ste_v1_build_eth_l2_dst_init, |
| .build_eth_l2_tnl_init = &dr_ste_v1_build_eth_l2_tnl_init, |
| .build_eth_l3_ipv4_misc_init = &dr_ste_v1_build_eth_l3_ipv4_misc_init, |
| .build_eth_ipv6_l3_l4_init = &dr_ste_v1_build_eth_ipv6_l3_l4_init, |
| .build_mpls_init = &dr_ste_v1_build_mpls_init, |
| .build_tnl_gre_init = &dr_ste_v1_build_tnl_gre_init, |
| .build_tnl_mpls_init = &dr_ste_v1_build_tnl_mpls_init, |
| .build_tnl_mpls_over_udp_init = &dr_ste_v1_build_tnl_mpls_over_udp_init, |
| .build_tnl_mpls_over_gre_init = &dr_ste_v1_build_tnl_mpls_over_gre_init, |
| .build_icmp_init = &dr_ste_v1_build_icmp_init, |
| .build_general_purpose_init = &dr_ste_v1_build_general_purpose_init, |
| .build_eth_l4_misc_init = &dr_ste_v1_build_eth_l4_misc_init, |
| .build_tnl_vxlan_gpe_init = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init, |
| .build_tnl_geneve_init = &dr_ste_v1_build_flex_parser_tnl_geneve_init, |
| .build_tnl_geneve_tlv_opt_init = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init, |
| .build_tnl_geneve_tlv_opt_exist_init = |
| &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init, |
| .build_register_0_init = &dr_ste_v1_build_register_0_init, |
| .build_register_1_init = &dr_ste_v1_build_register_1_init, |
| .build_src_gvmi_qpn_init = &dr_ste_v1_build_src_gvmi_qpn_init, |
| .build_flex_parser_0_init = &dr_ste_v1_build_flex_parser_0_init, |
| .build_flex_parser_1_init = &dr_ste_v1_build_flex_parser_1_init, |
| .build_tnl_gtpu_init = &dr_ste_v1_build_flex_parser_tnl_gtpu_init, |
| .build_tnl_header_0_1_init = &dr_ste_v1_build_tnl_header_0_1_init, |
| .build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init, |
| .build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init, |
| |
| /* Getters and Setters */ |
| .ste_init = &dr_ste_v1_init, |
| .set_next_lu_type = &dr_ste_v1_set_next_lu_type, |
| .get_next_lu_type = &dr_ste_v1_get_next_lu_type, |
| .is_miss_addr_set = &dr_ste_v1_is_miss_addr_set, |
| .set_miss_addr = &dr_ste_v1_set_miss_addr, |
| .get_miss_addr = &dr_ste_v1_get_miss_addr, |
| .set_hit_addr = &dr_ste_v1_set_hit_addr, |
| .set_byte_mask = &dr_ste_v1_set_byte_mask, |
| .get_byte_mask = &dr_ste_v1_get_byte_mask, |
| |
| /* Actions */ |
| .actions_caps = DR_STE_CTX_ACTION_CAP_TX_POP | |
| DR_STE_CTX_ACTION_CAP_RX_PUSH | |
| DR_STE_CTX_ACTION_CAP_RX_ENCAP, |
| .set_actions_rx = &dr_ste_v1_set_actions_rx, |
| .set_actions_tx = &dr_ste_v1_set_actions_tx, |
| .modify_field_arr_sz = ARRAY_SIZE(dr_ste_v2_action_modify_field_arr), |
| .modify_field_arr = dr_ste_v2_action_modify_field_arr, |
| .set_action_set = &dr_ste_v1_set_action_set, |
| .set_action_add = &dr_ste_v1_set_action_add, |
| .set_action_copy = &dr_ste_v1_set_action_copy, |
| .set_action_decap_l3_list = &dr_ste_v1_set_action_decap_l3_list, |
| |
| /* Send */ |
| .prepare_for_postsend = &dr_ste_v1_prepare_for_postsend, |
| }; |
| |
| struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v2(void) |
| { |
| return &ste_ctx_v2; |
| } |
