| /* |
| * MPC8544 DS Device Tree Source |
| * |
| * Copyright 2007 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| / { |
| model = "MPC8544DS"; |
| compatible = "MPC8544DS", "MPC85xxDS"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| ethernet0 = &enet0; |
| ethernet1 = &enet1; |
| serial0 = &serial0; |
| serial1 = &serial1; |
| pci0 = &pci0; |
| pci1 = &pci1; |
| pci2 = &pci2; |
| pci3 = &pci3; |
| }; |
| |
| cpus { |
| #cpus = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,8544@0 { |
| device_type = "cpu"; |
| reg = <0>; |
| d-cache-line-size = <20>; // 32 bytes |
| i-cache-line-size = <20>; // 32 bytes |
| d-cache-size = <8000>; // L1, 32K |
| i-cache-size = <8000>; // L1, 32K |
| timebase-frequency = <0>; |
| bus-frequency = <0>; |
| clock-frequency = <0>; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <00000000 00000000>; // Filled by U-Boot |
| }; |
| |
| soc8544@e0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "soc"; |
| |
| ranges = <00000000 e0000000 00100000>; |
| reg = <e0000000 00001000>; // CCSRBAR 1M |
| bus-frequency = <0>; // Filled out by uboot. |
| |
| memory-controller@2000 { |
| compatible = "fsl,8544-memory-controller"; |
| reg = <2000 1000>; |
| interrupt-parent = <&mpic>; |
| interrupts = <12 2>; |
| }; |
| |
| l2-cache-controller@20000 { |
| compatible = "fsl,8544-l2-cache-controller"; |
| reg = <20000 1000>; |
| cache-line-size = <20>; // 32 bytes |
| cache-size = <40000>; // L2, 256K |
| interrupt-parent = <&mpic>; |
| interrupts = <10 2>; |
| }; |
| |
| i2c@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <0>; |
| compatible = "fsl-i2c"; |
| reg = <3000 100>; |
| interrupts = <2b 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| i2c@3100 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cell-index = <1>; |
| compatible = "fsl-i2c"; |
| reg = <3100 100>; |
| interrupts = <2b 2>; |
| interrupt-parent = <&mpic>; |
| dfsrr; |
| }; |
| |
| mdio@24520 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,gianfar-mdio"; |
| reg = <24520 20>; |
| |
| phy0: ethernet-phy@0 { |
| interrupt-parent = <&mpic>; |
| interrupts = <a 1>; |
| reg = <0>; |
| device_type = "ethernet-phy"; |
| }; |
| phy1: ethernet-phy@1 { |
| interrupt-parent = <&mpic>; |
| interrupts = <a 1>; |
| reg = <1>; |
| device_type = "ethernet-phy"; |
| }; |
| }; |
| |
| enet0: ethernet@24000 { |
| cell-index = <0>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <24000 1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <1d 2 1e 2 22 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy0>; |
| phy-connection-type = "rgmii-id"; |
| }; |
| |
| enet1: ethernet@26000 { |
| cell-index = <1>; |
| device_type = "network"; |
| model = "TSEC"; |
| compatible = "gianfar"; |
| reg = <26000 1000>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <1f 2 20 2 21 2>; |
| interrupt-parent = <&mpic>; |
| phy-handle = <&phy1>; |
| phy-connection-type = "rgmii-id"; |
| }; |
| |
| serial0: serial@4500 { |
| cell-index = <0>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4500 100>; |
| clock-frequency = <0>; |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| serial1: serial@4600 { |
| cell-index = <1>; |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <4600 100>; |
| clock-frequency = <0>; |
| interrupts = <2a 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| global-utilities@e0000 { //global utilities block |
| compatible = "fsl,mpc8548-guts"; |
| reg = <e0000 1000>; |
| fsl,has-rstcr; |
| }; |
| |
| mpic: pic@40000 { |
| clock-frequency = <0>; |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| reg = <40000 40000>; |
| compatible = "chrp,open-pic"; |
| device_type = "open-pic"; |
| big-endian; |
| }; |
| }; |
| |
| pci0: pci@e0008000 { |
| cell-index = <0>; |
| compatible = "fsl,mpc8540-pci"; |
| device_type = "pci"; |
| interrupt-map-mask = <f800 0 0 7>; |
| interrupt-map = < |
| |
| /* IDSEL 0x11 J17 Slot 1 */ |
| 8800 0 0 1 &mpic 2 1 |
| 8800 0 0 2 &mpic 3 1 |
| 8800 0 0 3 &mpic 4 1 |
| 8800 0 0 4 &mpic 1 1 |
| |
| /* IDSEL 0x12 J16 Slot 2 */ |
| |
| 9000 0 0 1 &mpic 3 1 |
| 9000 0 0 2 &mpic 4 1 |
| 9000 0 0 3 &mpic 2 1 |
| 9000 0 0 4 &mpic 1 1>; |
| |
| interrupt-parent = <&mpic>; |
| interrupts = <18 2>; |
| bus-range = <0 ff>; |
| ranges = <02000000 0 c0000000 c0000000 0 20000000 |
| 01000000 0 00000000 e1000000 0 00010000>; |
| clock-frequency = <3f940aa>; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e0008000 1000>; |
| }; |
| |
| pci1: pcie@e0009000 { |
| cell-index = <1>; |
| compatible = "fsl,mpc8548-pcie"; |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e0009000 1000>; |
| bus-range = <0 ff>; |
| ranges = <02000000 0 80000000 80000000 0 20000000 |
| 01000000 0 00000000 e1010000 0 00010000>; |
| clock-frequency = <1fca055>; |
| interrupt-parent = <&mpic>; |
| interrupts = <1a 2>; |
| interrupt-map-mask = <f800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 4 1 |
| 0000 0 0 2 &mpic 5 1 |
| 0000 0 0 3 &mpic 6 1 |
| 0000 0 0 4 &mpic 7 1 |
| >; |
| pcie@0 { |
| reg = <0 0 0 0 0>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| ranges = <02000000 0 80000000 |
| 02000000 0 80000000 |
| 0 20000000 |
| |
| 01000000 0 00000000 |
| 01000000 0 00000000 |
| 0 00010000>; |
| }; |
| }; |
| |
| pci2: pcie@e000a000 { |
| cell-index = <2>; |
| compatible = "fsl,mpc8548-pcie"; |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e000a000 1000>; |
| bus-range = <0 ff>; |
| ranges = <02000000 0 a0000000 a0000000 0 10000000 |
| 01000000 0 00000000 e1020000 0 00010000>; |
| clock-frequency = <1fca055>; |
| interrupt-parent = <&mpic>; |
| interrupts = <19 2>; |
| interrupt-map-mask = <f800 0 0 7>; |
| interrupt-map = < |
| /* IDSEL 0x0 */ |
| 0000 0 0 1 &mpic 0 1 |
| 0000 0 0 2 &mpic 1 1 |
| 0000 0 0 3 &mpic 2 1 |
| 0000 0 0 4 &mpic 3 1 |
| >; |
| pcie@0 { |
| reg = <0 0 0 0 0>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| ranges = <02000000 0 a0000000 |
| 02000000 0 a0000000 |
| 0 10000000 |
| |
| 01000000 0 00000000 |
| 01000000 0 00000000 |
| 0 00010000>; |
| }; |
| }; |
| |
| pci3: pcie@e000b000 { |
| cell-index = <3>; |
| compatible = "fsl,mpc8548-pcie"; |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| reg = <e000b000 1000>; |
| bus-range = <0 ff>; |
| ranges = <02000000 0 b0000000 b0000000 0 00100000 |
| 01000000 0 00000000 b0100000 0 00100000>; |
| clock-frequency = <1fca055>; |
| interrupt-parent = <&mpic>; |
| interrupts = <1b 2>; |
| interrupt-map-mask = <ff00 0 0 1>; |
| interrupt-map = < |
| // IDSEL 0x1c USB |
| e000 0 0 1 &i8259 c 2 |
| e100 0 0 1 &i8259 9 2 |
| e200 0 0 1 &i8259 a 2 |
| e300 0 0 1 &i8259 b 2 |
| |
| // IDSEL 0x1d Audio |
| e800 0 0 1 &i8259 6 2 |
| |
| // IDSEL 0x1e Legacy |
| f000 0 0 1 &i8259 7 2 |
| f100 0 0 1 &i8259 7 2 |
| |
| // IDSEL 0x1f IDE/SATA |
| f800 0 0 1 &i8259 e 2 |
| f900 0 0 1 &i8259 5 2 |
| >; |
| |
| pcie@0 { |
| reg = <0 0 0 0 0>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| ranges = <02000000 0 b0000000 |
| 02000000 0 b0000000 |
| 0 00100000 |
| |
| 01000000 0 00000000 |
| 01000000 0 00000000 |
| 0 00100000>; |
| |
| uli1575@0 { |
| reg = <0 0 0 0 0>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| ranges = <02000000 0 b0000000 |
| 02000000 0 b0000000 |
| 0 00100000 |
| |
| 01000000 0 00000000 |
| 01000000 0 00000000 |
| 0 00100000>; |
| isa@1e { |
| device_type = "isa"; |
| #interrupt-cells = <2>; |
| #size-cells = <1>; |
| #address-cells = <2>; |
| reg = <f000 0 0 0 0>; |
| ranges = <1 0 |
| 01000000 0 0 |
| 00001000>; |
| interrupt-parent = <&i8259>; |
| |
| i8259: interrupt-controller@20 { |
| reg = <1 20 2 |
| 1 a0 2 |
| 1 4d0 2>; |
| interrupt-controller; |
| device_type = "interrupt-controller"; |
| #address-cells = <0>; |
| #interrupt-cells = <2>; |
| compatible = "chrp,iic"; |
| interrupts = <9 2>; |
| interrupt-parent = <&mpic>; |
| }; |
| |
| i8042@60 { |
| #size-cells = <0>; |
| #address-cells = <1>; |
| reg = <1 60 1 1 64 1>; |
| interrupts = <1 3 c 3>; |
| interrupt-parent = <&i8259>; |
| |
| keyboard@0 { |
| reg = <0>; |
| compatible = "pnpPNP,303"; |
| }; |
| |
| mouse@1 { |
| reg = <1>; |
| compatible = "pnpPNP,f03"; |
| }; |
| }; |
| |
| rtc@70 { |
| compatible = "pnpPNP,b00"; |
| reg = <1 70 2>; |
| }; |
| |
| gpio@400 { |
| reg = <1 400 80>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| }; |
