arch/arm/boot/dts/intel-ixp4xx.dtsi

// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Intel XScale Network Processors
 * in the IXP 4xx series.
 */
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";
		interrupt-parent = <&intcon>;

		qmgr: queue-manager@60000000 {
			compatible = "intel,ixp4xx-ahb-queue-manager";
			reg = <0x60000000 0x4000>;
			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
		};

		uart0: serial@c8000000 {
			compatible = "intel,xscale-uart";
			reg = <0xc8000000 0x1000>;
			/*
			 * The reg-offset and reg-shift is a side effect
			 * of running the platform in big endian mode.
			 */
			reg-offset = <3>;
			reg-shift = <2>;
			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <14745600>;
			no-loopback-test;
		};

		gpio0: gpio@c8004000 {
			compatible = "intel,ixp4xx-gpio";
			reg = <0xc8004000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		intcon: interrupt-controller@c8003000 {
			/*
			 * Note: no compatible string. The subvariant of the
			 * chip needs to define what version it is. The
			 * location of the interrupt controller is fixed in
			 * memory across all variants.
			 */
			reg = <0xc8003000 0x100>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@c8005000 {
			compatible = "intel,ixp4xx-timer";
			reg = <0xc8005000 0x100>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
		};

		npe@c8006000 {
			compatible = "intel,ixp4xx-network-processing-engine";
			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
		};
	};
};