Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX8M DDR Controller

maintainers:
  - Leonard Crestez <leonard.crestez@nxp.com>

description:
  The DDRC block is integrated in i.MX8M for interfacing with DDR based
  memories.

  It supports switching between different frequencies at runtime but during
  this process RAM itself becomes briefly inaccessible so actual frequency
  switching is implemented by TF-A code which runs from a SRAM area.

  The Linux driver for the DDRC doesn't even map registers (they're included
  for the sake of "describing hardware"), it mostly just exposes firmware
  capabilities through standard Linux mechanism like devfreq and OPP tables.

properties:
  compatible:
    items:
      - enum:
          - fsl,imx8mn-ddrc
          - fsl,imx8mm-ddrc
          - fsl,imx8mq-ddrc
      - const: fsl,imx8m-ddrc

  reg:
    maxItems: 1
    description:
      Base address and size of DDRC CTL area.
      This is not currently mapped by the imx8m-ddrc driver.

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: core
      - const: pll
      - const: alt
      - const: apb

  operating-points-v2: true
  opp-table: true

required:
  - reg
  - compatible
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    ddrc: memory-controller@3d400000 {
        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
        reg = <0x3d400000 0x400000>;
        clock-names = "core", "pll", "alt", "apb";
        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
                 <&clk IMX8MM_DRAM_PLL>,
                 <&clk IMX8MM_CLK_DRAM_ALT>,
                 <&clk IMX8MM_CLK_DRAM_APB>;
        operating-points-v2 = <&ddrc_opp_table>;
    };