| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2020 Gateworks Corporation |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/linux-event-codes.h> |
| #include <dt-bindings/leds/common.h> |
| #include <dt-bindings/phy/phy-imx8-pcie.h> |
| |
| #include "imx8mm.dtsi" |
| |
| / { |
| model = "Gateworks Venice GW7901 i.MX8MM board"; |
| compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; |
| |
| aliases { |
| ethernet0 = &fec1; |
| ethernet1 = &lan1; |
| ethernet2 = &lan2; |
| ethernet3 = &lan3; |
| ethernet4 = &lan4; |
| usb0 = &usbotg1; |
| usb1 = &usbotg2; |
| }; |
| |
| chosen { |
| stdout-path = &uart2; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x0 0x40000000 0 0x80000000>; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| |
| key-user-pb { |
| label = "user_pb"; |
| gpios = <&gpio 2 GPIO_ACTIVE_LOW>; |
| linux,code = <BTN_0>; |
| }; |
| |
| key-user-pb1x { |
| label = "user_pb1x"; |
| linux,code = <BTN_1>; |
| interrupt-parent = <&gsc>; |
| interrupts = <0>; |
| }; |
| |
| key-erased { |
| label = "key_erased"; |
| linux,code = <BTN_2>; |
| interrupt-parent = <&gsc>; |
| interrupts = <1>; |
| }; |
| |
| key-eeprom-wp { |
| label = "eeprom_wp"; |
| linux,code = <BTN_3>; |
| interrupt-parent = <&gsc>; |
| interrupts = <2>; |
| }; |
| |
| key-tamper { |
| label = "tamper"; |
| linux,code = <BTN_4>; |
| interrupt-parent = <&gsc>; |
| interrupts = <5>; |
| }; |
| |
| switch-hold { |
| label = "switch_hold"; |
| linux,code = <BTN_5>; |
| interrupt-parent = <&gsc>; |
| interrupts = <7>; |
| }; |
| }; |
| |
| led-controller { |
| compatible = "gpio-leds"; |
| |
| led-0 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_RED>; |
| label = "led01_red"; |
| gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-1 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "led01_grn"; |
| gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-2 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_RED>; |
| label = "led02_red"; |
| gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-3 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "led02_grn"; |
| gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-4 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_RED>; |
| label = "led03_red"; |
| gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-5 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "led03_grn"; |
| gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-6 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_RED>; |
| label = "led04_red"; |
| gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-7 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "led04_grn"; |
| gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-8 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_RED>; |
| label = "led05_red"; |
| gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-9 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "led05_grn"; |
| gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-a { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_RED>; |
| label = "led06_red"; |
| gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| led-b { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "led06_grn"; |
| gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| }; |
| |
| pcie0_refclk: pcie0-refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "3P3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| regulator-ioexp { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_ioexp>; |
| compatible = "regulator-fixed"; |
| regulator-name = "ioexp"; |
| gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| startup-delay-us = <100>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| regulator-isouart { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_isouart>; |
| compatible = "regulator-fixed"; |
| regulator-name = "iso_uart"; |
| gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; |
| startup-delay-us = <100>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| reg_usb2_vbus: regulator-usb2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usb2>; |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_usb2_vbus"; |
| gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| }; |
| |
| reg_wifi: regulator-wifi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_wl>; |
| compatible = "regulator-fixed"; |
| regulator-name = "wifi"; |
| gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| startup-delay-us = <100>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-25000000 { |
| opp-hz = /bits/ 64 <25000000>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| |
| opp-750000000 { |
| opp-hz = /bits/ 64 <750000000>; |
| }; |
| }; |
| }; |
| |
| &disp_blk_ctrl { |
| status = "disabled"; |
| }; |
| |
| &ecspi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi1>; |
| cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <40000000>; |
| status = "okay"; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| local-mac-address = [00 00 00 00 00 00]; |
| status = "okay"; |
| |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| }; |
| }; |
| |
| &gpio1 { |
| gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", |
| "", "uart1_rs232#", "dig1_in", "dig1_out", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpio4 { |
| gpio-line-names = "", "", "", "", |
| "", "", "uart3_rs232#", "uart3_rs422#", |
| "uart3_rs485#", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; |
| }; |
| |
| &gpio5 { |
| gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", |
| "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpu_2d { |
| status = "disabled"; |
| }; |
| |
| &gpu_3d { |
| status = "disabled"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| gsc: gsc@20 { |
| compatible = "gw,gsc"; |
| reg = <0x20>; |
| pinctrl-0 = <&pinctrl_gsc>; |
| interrupt-parent = <&gpio4>; |
| interrupts = <16 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| adc { |
| compatible = "gw,gsc-adc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| channel@6 { |
| gw,mode = <0>; |
| reg = <0x06>; |
| label = "temp"; |
| }; |
| |
| channel@8 { |
| gw,mode = <1>; |
| reg = <0x08>; |
| label = "vdd_bat"; |
| }; |
| |
| channel@82 { |
| gw,mode = <2>; |
| reg = <0x82>; |
| label = "vin_aux1"; |
| gw,voltage-divider-ohms = <22100 1000>; |
| }; |
| |
| channel@84 { |
| gw,mode = <2>; |
| reg = <0x84>; |
| label = "vin_aux2"; |
| gw,voltage-divider-ohms = <22100 1000>; |
| }; |
| |
| channel@86 { |
| gw,mode = <2>; |
| reg = <0x86>; |
| label = "vdd_vin"; |
| gw,voltage-divider-ohms = <22100 1000>; |
| }; |
| |
| channel@88 { |
| gw,mode = <2>; |
| reg = <0x88>; |
| label = "vdd_3p3"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@8c { |
| gw,mode = <2>; |
| reg = <0x8c>; |
| label = "vdd_2p5"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@8e { |
| gw,mode = <2>; |
| reg = <0x8e>; |
| label = "vdd_0p95"; |
| }; |
| |
| channel@90 { |
| gw,mode = <2>; |
| reg = <0x90>; |
| label = "vdd_soc"; |
| }; |
| |
| channel@92 { |
| gw,mode = <2>; |
| reg = <0x92>; |
| label = "vdd_arm"; |
| }; |
| |
| channel@98 { |
| gw,mode = <2>; |
| reg = <0x98>; |
| label = "vdd_1p8"; |
| }; |
| |
| channel@9a { |
| gw,mode = <2>; |
| reg = <0x9a>; |
| label = "vdd_1p2"; |
| }; |
| |
| channel@9c { |
| gw,mode = <2>; |
| reg = <0x9c>; |
| label = "vdd_dram"; |
| }; |
| |
| channel@a2 { |
| gw,mode = <2>; |
| reg = <0xa2>; |
| label = "vdd_gsc"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| }; |
| }; |
| |
| gpio: gpio@23 { |
| compatible = "nxp,pca9555"; |
| reg = <0x23>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gsc>; |
| interrupts = <4>; |
| }; |
| |
| eeprom@50 { |
| compatible = "atmel,24c02"; |
| reg = <0x50>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@51 { |
| compatible = "atmel,24c02"; |
| reg = <0x51>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@52 { |
| compatible = "atmel,24c02"; |
| reg = <0x52>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@53 { |
| compatible = "atmel,24c02"; |
| reg = <0x53>; |
| pagesize = <16>; |
| }; |
| |
| rtc@68 { |
| compatible = "dallas,ds1672"; |
| reg = <0x68>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| pmic@4b { |
| compatible = "rohm,bd71847"; |
| reg = <0x4b>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <20 IRQ_TYPE_LEVEL_LOW>; |
| rohm,reset-snvs-powered; |
| #clock-cells = <0>; |
| clocks = <&osc_32k 0>; |
| clock-output-names = "clk-32k-out"; |
| |
| regulators { |
| /* vdd_soc: 0.805-0.900V (typ=0.8V) */ |
| BUCK1 { |
| regulator-name = "buck1"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| /* vdd_arm: 0.805-1.0V (typ=0.9V) */ |
| BUCK2 { |
| regulator-name = "buck2"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <1000000>; |
| rohm,dvs-idle-voltage = <900000>; |
| }; |
| |
| /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ |
| BUCK3 { |
| regulator-name = "buck3"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_3p3 */ |
| BUCK4 { |
| regulator-name = "buck4"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_1p8 */ |
| BUCK5 { |
| regulator-name = "buck5"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_dram */ |
| BUCK6 { |
| regulator-name = "buck6"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* nvcc_snvs_1p8 */ |
| LDO1 { |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1600000>; |
| regulator-max-microvolt = <1900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_snvs_0p8 */ |
| LDO2 { |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdda_1p8 */ |
| LDO3 { |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| LDO4 { |
| regulator-name = "ldo4"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| LDO6 { |
| regulator-name = "ldo6"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| pinctrl-1 = <&pinctrl_i2c3_gpio>; |
| scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| leds_gpio: gpio@20 { |
| compatible = "nxp,pca9555"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| switch: switch@5f { |
| compatible = "microchip,ksz9897"; |
| reg = <0x5f>; |
| pinctrl-0 = <&pinctrl_ksz>; |
| interrupt-parent = <&gpio4>; |
| interrupts = <18 IRQ_TYPE_EDGE_FALLING>; |
| phy-mode = "rgmii-id"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| lan1: port@0 { |
| reg = <0>; |
| label = "lan1"; |
| phy-mode = "internal"; |
| local-mac-address = [00 00 00 00 00 00]; |
| }; |
| |
| lan2: port@1 { |
| reg = <1>; |
| label = "lan2"; |
| phy-mode = "internal"; |
| local-mac-address = [00 00 00 00 00 00]; |
| }; |
| |
| lan3: port@2 { |
| reg = <2>; |
| label = "lan3"; |
| phy-mode = "internal"; |
| local-mac-address = [00 00 00 00 00 00]; |
| }; |
| |
| lan4: port@3 { |
| reg = <3>; |
| label = "lan4"; |
| phy-mode = "internal"; |
| local-mac-address = [00 00 00 00 00 00]; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| label = "cpu"; |
| ethernet = <&fec1>; |
| phy-mode = "rgmii-id"; |
| |
| fixed-link { |
| speed = <1000>; |
| full-duplex; |
| }; |
| }; |
| }; |
| }; |
| |
| crypto@60 { |
| compatible = "atmel,atecc508a"; |
| reg = <0x60>; |
| }; |
| }; |
| |
| &i2c4 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c4>; |
| pinctrl-1 = <&pinctrl_i2c4_gpio>; |
| scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| &pcie_phy { |
| fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; |
| fsl,clkreq-unsupported; |
| clocks = <&pcie0_refclk>; |
| clock-names = "ref"; |
| status = "okay"; |
| }; |
| |
| &pcie0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0>; |
| reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; |
| clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, |
| <&clk IMX8MM_CLK_PCIE1_AUX>; |
| assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, |
| <&clk IMX8MM_CLK_PCIE1_CTRL>; |
| assigned-clock-rates = <10000000>, <250000000>; |
| assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, |
| <&clk IMX8MM_SYS_PLL2_250M>; |
| status = "okay"; |
| }; |
| |
| &pgc_gpu { |
| status = "disabled"; |
| }; |
| |
| &pgc_gpumix { |
| status = "disabled"; |
| }; |
| |
| &pgc_mipi { |
| status = "disabled"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; |
| rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; |
| cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; |
| dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; |
| dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
| dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| /* console */ |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; |
| cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; |
| rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; |
| cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; |
| rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| dr_mode = "host"; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| dr_mode = "host"; |
| vbus-supply = <®_usb2_vbus>; |
| over-current-active-low; |
| status = "okay"; |
| }; |
| |
| /* SDIO WiFi */ |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <4>; |
| non-removable; |
| vmmc-supply = <®_wifi>; |
| status = "okay"; |
| }; |
| |
| /* microSD */ |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| bus-width = <4>; |
| vmmc-supply = <®_3p3v>; |
| status = "okay"; |
| }; |
| |
| /* eMMC */ |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ |
| MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ |
| MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ |
| MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ |
| MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ |
| MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ |
| MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 |
| MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ |
| MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ |
| >; |
| }; |
| |
| pinctrl_gsc: gscgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3_gpio: i2c3gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c4: i2c4grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c4_gpio: i2c4gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 |
| MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_ksz: kszgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 |
| MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ |
| >; |
| }; |
| |
| pinctrl_pcie0: pciegrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ |
| MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 |
| >; |
| }; |
| |
| pinctrl_reg_isouart: regisouartgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 |
| >; |
| }; |
| |
| pinctrl_reg_ioexp: regioexpgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 |
| >; |
| }; |
| |
| pinctrl_reg_wl: regwlgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 |
| >; |
| }; |
| |
| pinctrl_reg_usb2: regusb1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 |
| MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 |
| MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 |
| >; |
| }; |
| |
| pinctrl_spi1: spi1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 |
| MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 |
| MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 |
| MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 |
| MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 |
| MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 |
| MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 |
| MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 |
| MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 |
| >; |
| }; |
| |
| pinctrl_uart1_gpio: uart1gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ |
| MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ |
| MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 |
| MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 |
| MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 |
| >; |
| }; |
| |
| pinctrl_uart3_gpio: uart3gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ |
| MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ |
| MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ |
| >; |
| }; |
| |
| pinctrl_uart4: uart4grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 |
| MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 |
| MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 |
| >; |
| }; |
| |
| pinctrl_uart4_gpio: uart4gpiogrp { |
| fsl,pins = < |
| |
| MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ |
| MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ |
| MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2-gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |
