| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2019 NXP |
| */ |
| |
| #include <dt-bindings/clock/imx8mp-clock.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| #include "imx8mp-pinfunc.h" |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| ethernet0 = &fec; |
| gpio0 = &gpio1; |
| gpio1 = &gpio2; |
| gpio2 = &gpio3; |
| gpio3 = &gpio4; |
| gpio4 = &gpio5; |
| i2c0 = &i2c1; |
| i2c1 = &i2c2; |
| i2c2 = &i2c3; |
| i2c3 = &i2c4; |
| i2c4 = &i2c5; |
| i2c5 = &i2c6; |
| mmc0 = &usdhc1; |
| mmc1 = &usdhc2; |
| mmc2 = &usdhc3; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| A53_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| clock-latency = <61036>; |
| clocks = <&clk IMX8MP_CLK_ARM>; |
| enable-method = "psci"; |
| next-level-cache = <&A53_L2>; |
| #cooling-cells = <2>; |
| }; |
| |
| A53_1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| clock-latency = <61036>; |
| clocks = <&clk IMX8MP_CLK_ARM>; |
| enable-method = "psci"; |
| next-level-cache = <&A53_L2>; |
| #cooling-cells = <2>; |
| }; |
| |
| A53_2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x2>; |
| clock-latency = <61036>; |
| clocks = <&clk IMX8MP_CLK_ARM>; |
| enable-method = "psci"; |
| next-level-cache = <&A53_L2>; |
| #cooling-cells = <2>; |
| }; |
| |
| A53_3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x3>; |
| clock-latency = <61036>; |
| clocks = <&clk IMX8MP_CLK_ARM>; |
| enable-method = "psci"; |
| next-level-cache = <&A53_L2>; |
| #cooling-cells = <2>; |
| }; |
| |
| A53_L2: l2-cache0 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| osc_32k: clock-osc-32k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| clock-output-names = "osc_32k"; |
| }; |
| |
| osc_24m: clock-osc-24m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "osc_24m"; |
| }; |
| |
| clk_ext1: clock-ext1 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <133000000>; |
| clock-output-names = "clk_ext1"; |
| }; |
| |
| clk_ext2: clock-ext2 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <133000000>; |
| clock-output-names = "clk_ext2"; |
| }; |
| |
| clk_ext3: clock-ext3 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <133000000>; |
| clock-output-names = "clk_ext3"; |
| }; |
| |
| clk_ext4: clock-ext4 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency= <133000000>; |
| clock-output-names = "clk_ext4"; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| thermal-zones { |
| cpu-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <2000>; |
| thermal-sensors = <&tmu 0>; |
| trips { |
| cpu_alert0: trip0 { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit0: trip1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu_alert0>; |
| cooling-device = |
| <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| soc-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <2000>; |
| thermal-sensors = <&tmu 1>; |
| trips { |
| soc_alert0: trip0 { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| soc_crit0: trip1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&soc_alert0>; |
| cooling-device = |
| <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| clock-frequency = <8000000>; |
| arm,no-tick-in-suspend; |
| }; |
| |
| soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x0 0x3e000000>; |
| |
| aips1: bus@30000000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0x30000000 0x400000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| gpio1: gpio@30200000 { |
| compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; |
| reg = <0x30200000 0x10000>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 5 30>; |
| }; |
| |
| gpio2: gpio@30210000 { |
| compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; |
| reg = <0x30210000 0x10000>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 35 21>; |
| }; |
| |
| gpio3: gpio@30220000 { |
| compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; |
| reg = <0x30220000 0x10000>; |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>; |
| }; |
| |
| gpio4: gpio@30230000 { |
| compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; |
| reg = <0x30230000 0x10000>; |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 82 32>; |
| }; |
| |
| gpio5: gpio@30240000 { |
| compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; |
| reg = <0x30240000 0x10000>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 114 30>; |
| }; |
| |
| tmu: tmu@30260000 { |
| compatible = "fsl,imx8mp-tmu"; |
| reg = <0x30260000 0x10000>; |
| clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| wdog1: watchdog@30280000 { |
| compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; |
| reg = <0x30280000 0x10000>; |
| interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; |
| status = "disabled"; |
| }; |
| |
| iomuxc: pinctrl@30330000 { |
| compatible = "fsl,imx8mp-iomuxc"; |
| reg = <0x30330000 0x10000>; |
| }; |
| |
| gpr: iomuxc-gpr@30340000 { |
| compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; |
| reg = <0x30340000 0x10000>; |
| }; |
| |
| ocotp: efuse@30350000 { |
| compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; |
| reg = <0x30350000 0x10000>; |
| clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; |
| /* For nvmem subnodes */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpu_speed_grade: speed-grade@10 { |
| reg = <0x10 4>; |
| }; |
| }; |
| |
| anatop: anatop@30360000 { |
| compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", |
| "syscon"; |
| reg = <0x30360000 0x10000>; |
| }; |
| |
| snvs: snvs@30370000 { |
| compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; |
| reg = <0x30370000 0x10000>; |
| |
| snvs_rtc: snvs-rtc-lp { |
| compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| regmap =<&snvs>; |
| offset = <0x34>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; |
| clock-names = "snvs-rtc"; |
| }; |
| |
| snvs_pwrkey: snvs-powerkey { |
| compatible = "fsl,sec-v4.0-pwrkey"; |
| regmap = <&snvs>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; |
| clock-names = "snvs-pwrkey"; |
| linux,keycode = <KEY_POWER>; |
| wakeup-source; |
| status = "disabled"; |
| }; |
| }; |
| |
| clk: clock-controller@30380000 { |
| compatible = "fsl,imx8mp-ccm"; |
| reg = <0x30380000 0x10000>; |
| #clock-cells = <1>; |
| clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, |
| <&clk_ext3>, <&clk_ext4>; |
| clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", |
| "clk_ext3", "clk_ext4"; |
| assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, |
| <&clk IMX8MP_CLK_A53_CORE>, |
| <&clk IMX8MP_CLK_NOC>, |
| <&clk IMX8MP_CLK_NOC_IO>, |
| <&clk IMX8MP_CLK_GIC>, |
| <&clk IMX8MP_CLK_AUDIO_AHB>, |
| <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, |
| <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, |
| <&clk IMX8MP_AUDIO_PLL1>, |
| <&clk IMX8MP_AUDIO_PLL2>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, |
| <&clk IMX8MP_ARM_PLL_OUT>, |
| <&clk IMX8MP_SYS_PLL2_1000M>, |
| <&clk IMX8MP_SYS_PLL1_800M>, |
| <&clk IMX8MP_SYS_PLL2_500M>, |
| <&clk IMX8MP_SYS_PLL1_800M>, |
| <&clk IMX8MP_SYS_PLL1_800M>; |
| assigned-clock-rates = <0>, <0>, |
| <1000000000>, |
| <800000000>, |
| <500000000>, |
| <400000000>, |
| <800000000>, |
| <400000000>, |
| <393216000>, |
| <361267200>; |
| }; |
| |
| src: reset-controller@30390000 { |
| compatible = "fsl,imx8mp-src", "syscon"; |
| reg = <0x30390000 0x10000>; |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| aips2: bus@30400000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0x30400000 0x400000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| pwm1: pwm@30660000 { |
| compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; |
| reg = <0x30660000 0x10000>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, |
| <&clk IMX8MP_CLK_PWM1_ROOT>; |
| clock-names = "ipg", "per"; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm2: pwm@30670000 { |
| compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; |
| reg = <0x30670000 0x10000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, |
| <&clk IMX8MP_CLK_PWM2_ROOT>; |
| clock-names = "ipg", "per"; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm3: pwm@30680000 { |
| compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; |
| reg = <0x30680000 0x10000>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, |
| <&clk IMX8MP_CLK_PWM3_ROOT>; |
| clock-names = "ipg", "per"; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm4: pwm@30690000 { |
| compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; |
| reg = <0x30690000 0x10000>; |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, |
| <&clk IMX8MP_CLK_PWM4_ROOT>; |
| clock-names = "ipg", "per"; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| system_counter: timer@306a0000 { |
| compatible = "nxp,sysctr-timer"; |
| reg = <0x306a0000 0x20000>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc_24m>; |
| clock-names = "per"; |
| }; |
| }; |
| |
| aips3: bus@30800000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| reg = <0x30800000 0x400000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| ecspi1: spi@30820000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x30820000 0x10000>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, |
| <&clk IMX8MP_CLK_ECSPI1_ROOT>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ecspi2: spi@30830000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x30830000 0x10000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, |
| <&clk IMX8MP_CLK_ECSPI2_ROOT>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ecspi3: spi@30840000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x30840000 0x10000>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, |
| <&clk IMX8MP_CLK_ECSPI3_ROOT>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@30860000 { |
| compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; |
| reg = <0x30860000 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_UART1_ROOT>, |
| <&clk IMX8MP_CLK_UART1_ROOT>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@30880000 { |
| compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; |
| reg = <0x30880000 0x10000>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_UART3_ROOT>, |
| <&clk IMX8MP_CLK_UART3_ROOT>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@30890000 { |
| compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; |
| reg = <0x30890000 0x10000>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_UART2_ROOT>, |
| <&clk IMX8MP_CLK_UART2_ROOT>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| flexcan1: can@308c0000 { |
| compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; |
| reg = <0x308c0000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_IPG_ROOT>, |
| <&clk IMX8MP_CLK_CAN1_ROOT>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&clk IMX8MP_CLK_CAN1>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; |
| assigned-clock-rates = <40000000>; |
| fsl,clk-source = /bits/ 8 <0>; |
| fsl,stop-mode = <&gpr 0x10 4>; |
| status = "disabled"; |
| }; |
| |
| flexcan2: can@308d0000 { |
| compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; |
| reg = <0x308d0000 0x10000>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_IPG_ROOT>, |
| <&clk IMX8MP_CLK_CAN2_ROOT>; |
| clock-names = "ipg", "per"; |
| assigned-clocks = <&clk IMX8MP_CLK_CAN2>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; |
| assigned-clock-rates = <40000000>; |
| fsl,clk-source = /bits/ 8 <0>; |
| fsl,stop-mode = <&gpr 0x10 5>; |
| status = "disabled"; |
| }; |
| |
| crypto: crypto@30900000 { |
| compatible = "fsl,sec-v4.0"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x30900000 0x40000>; |
| ranges = <0 0x30900000 0x40000>; |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_AHB>, |
| <&clk IMX8MP_CLK_IPG_ROOT>; |
| clock-names = "aclk", "ipg"; |
| |
| sec_jr0: jr@1000 { |
| compatible = "fsl,sec-v4.0-job-ring"; |
| reg = <0x1000 0x1000>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr1: jr@2000 { |
| compatible = "fsl,sec-v4.0-job-ring"; |
| reg = <0x2000 0x1000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr2: jr@3000 { |
| compatible = "fsl,sec-v4.0-job-ring"; |
| reg = <0x3000 0x1000>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| i2c1: i2c@30a20000 { |
| compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a20000 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@30a30000 { |
| compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a30000 0x10000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@30a40000 { |
| compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a40000 0x10000>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@30a50000 { |
| compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a50000 0x10000>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@30a60000 { |
| compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; |
| reg = <0x30a60000 0x10000>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_UART4_ROOT>, |
| <&clk IMX8MP_CLK_UART4_ROOT>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| mu: mailbox@30aa0000 { |
| compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; |
| reg = <0x30aa0000 0x10000>; |
| interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_MU_ROOT>; |
| #mbox-cells = <2>; |
| }; |
| |
| i2c5: i2c@30ad0000 { |
| compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30ad0000 0x10000>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@30ae0000 { |
| compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30ae0000 0x10000>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; |
| status = "disabled"; |
| }; |
| |
| usdhc1: mmc@30b40000 { |
| compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; |
| reg = <0x30b40000 0x10000>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_DUMMY>, |
| <&clk IMX8MP_CLK_NAND_USDHC_BUS>, |
| <&clk IMX8MP_CLK_USDHC1_ROOT>; |
| clock-names = "ipg", "ahb", "per"; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step= <2>; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: mmc@30b50000 { |
| compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; |
| reg = <0x30b50000 0x10000>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_DUMMY>, |
| <&clk IMX8MP_CLK_NAND_USDHC_BUS>, |
| <&clk IMX8MP_CLK_USDHC2_ROOT>; |
| clock-names = "ipg", "ahb", "per"; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step= <2>; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: mmc@30b60000 { |
| compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; |
| reg = <0x30b60000 0x10000>; |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_DUMMY>, |
| <&clk IMX8MP_CLK_NAND_USDHC_BUS>, |
| <&clk IMX8MP_CLK_USDHC3_ROOT>; |
| clock-names = "ipg", "ahb", "per"; |
| fsl,tuning-start-tap = <20>; |
| fsl,tuning-step= <2>; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| sdma1: dma-controller@30bd0000 { |
| compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; |
| reg = <0x30bd0000 0x10000>; |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, |
| <&clk IMX8MP_CLK_AHB>; |
| clock-names = "ipg", "ahb"; |
| #dma-cells = <3>; |
| fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; |
| }; |
| |
| fec: ethernet@30be0000 { |
| compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; |
| reg = <0x30be0000 0x10000>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, |
| <&clk IMX8MP_CLK_SIM_ENET_ROOT>, |
| <&clk IMX8MP_CLK_ENET_TIMER>, |
| <&clk IMX8MP_CLK_ENET_REF>, |
| <&clk IMX8MP_CLK_ENET_PHY_REF>; |
| clock-names = "ipg", "ahb", "ptp", |
| "enet_clk_ref", "enet_out"; |
| assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, |
| <&clk IMX8MP_CLK_ENET_TIMER>, |
| <&clk IMX8MP_CLK_ENET_REF>, |
| <&clk IMX8MP_CLK_ENET_TIMER>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, |
| <&clk IMX8MP_SYS_PLL2_100M>, |
| <&clk IMX8MP_SYS_PLL2_125M>; |
| assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; |
| fsl,num-tx-queues = <3>; |
| fsl,num-rx-queues = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| gic: interrupt-controller@38800000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x38800000 0x10000>, |
| <0x38880000 0xc0000>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| ddr-pmu@3d800000 { |
| compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; |
| reg = <0x3d800000 0x400000>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| }; |
