drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c - linux - Git at Google

 /*
  * Copyright 2020 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: AMD
  *
  */

 #include "reg_helper.h"
 #include "dcn301_optc.h"
 #include "dc.h"
 #include "dcn_calc_math.h"
 #include "dc_dmub_srv.h"

 #include "dml/dcn30/dcn30_fpu.h"
 #include "dc_trace.h"

 #define REG(reg)\
 	optc1->tg_regs->reg

 #define CTX \
 	optc1->base.ctx

 #undef FN
 #define FN(reg_name, field_name) \
 	optc1->tg_shift->field_name, optc1->tg_mask->field_name


 /**
  * optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
  *
  * @optc: timing_generator instance.
  * @params: parameters used for Dynamic Refresh Rate.
  */
 void optc301_set_drr(
 	struct timing_generator *optc,
 	const struct drr_params *params)
 {
 	struct optc *optc1 = DCN10TG_FROM_TG(optc);

 	if (params != NULL &&
 		params->vertical_total_max > 0 &&
 		params->vertical_total_min > 0) {

 		if (params->vertical_total_mid != 0) {

 			REG_SET(OTG_V_TOTAL_MID, 0,
 				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);

 			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
 					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
 					OTG_VTOTAL_MID_FRAME_NUM,
 					(uint8_t)params->vertical_total_mid_frame_num);

 		}

 		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

 		REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
 				OTG_V_TOTAL_MIN_SEL, 1,
 				OTG_V_TOTAL_MAX_SEL, 1,
 				OTG_FORCE_LOCK_ON_EVENT, 0,
 				OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
 				OTG_SET_V_TOTAL_MIN_MASK, 0);
 		// Setup manual flow control for EOF via TRIG_A
 		optc->funcs->setup_manual_trigger(optc);

 	} else {
 		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
 				OTG_SET_V_TOTAL_MIN_MASK, 0,
 				OTG_V_TOTAL_MIN_SEL, 0,
 				OTG_V_TOTAL_MAX_SEL, 0,
 				OTG_FORCE_LOCK_ON_EVENT, 0);

 		optc->funcs->set_vtotal_min_max(optc, 0, 0);
 	}
 }


 void optc301_setup_manual_trigger(struct timing_generator *optc)
 {
 	struct optc *optc1 = DCN10TG_FROM_TG(optc);

 	REG_SET_8(OTG_TRIGA_CNTL, 0,
 			OTG_TRIGA_SOURCE_SELECT, 21,
 			OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
 			OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
 			OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
 			OTG_TRIGA_POLARITY_SELECT, 0,
 			OTG_TRIGA_FREQUENCY_SELECT, 0,
 			OTG_TRIGA_DELAY, 0,
 			OTG_TRIGA_CLEAR, 1);
 }

 static struct timing_generator_funcs dcn30_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
 		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
 		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
 		.program_global_sync = optc1_program_global_sync,
 		.enable_crtc = optc2_enable_crtc,
 		.disable_crtc = optc1_disable_crtc,
 		/* used by enable_timing_synchronization. Not need for FPGA */
 		.is_counter_moving = optc1_is_counter_moving,
 		.get_position = optc1_get_position,
 		.get_frame_count = optc1_get_vblank_counter,
 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
 		.get_otg_active_size = optc1_get_otg_active_size,
 		.set_early_control = optc1_set_early_control,
 		/* used by enable_timing_synchronization. Not need for FPGA */
 		.wait_for_state = optc1_wait_for_state,
 		.set_blank_color = optc3_program_blank_color,
 		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
 		.triplebuffer_lock = optc3_triplebuffer_lock,
 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
 		.enable_reset_trigger = optc1_enable_reset_trigger,
 		.enable_crtc_reset = optc1_enable_crtc_reset,
 		.disable_reset_trigger = optc1_disable_reset_trigger,
 		.lock = optc3_lock,
 		.unlock = optc1_unlock,
 		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc301_set_drr,
 		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_vtotal_min_max = optc3_set_vtotal_min_max,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
 		.tg_init = optc3_tg_init,
 		.is_tg_enabled = optc1_is_tg_enabled,
 		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
 		.clear_optc_underflow = optc1_clear_optc_underflow,
 		.setup_global_swap_lock = NULL,
 		.get_crc = optc1_get_crc,
 		.configure_crc = optc2_configure_crc,
 		.set_dsc_config = optc3_set_dsc_config,
 		.get_dsc_status = optc2_get_dsc_status,
 		.set_dwb_source = NULL,
 		.set_odm_bypass = optc3_set_odm_bypass,
 		.set_odm_combine = optc3_set_odm_combine,
 		.get_optc_source = optc2_get_optc_source,
 		.set_out_mux = optc3_set_out_mux,
 		.set_drr_trigger_window = optc3_set_drr_trigger_window,
 		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
 		.set_gsl = optc2_set_gsl,
 		.set_gsl_source_select = optc2_set_gsl_source_select,
 		.set_vtg_params = optc1_set_vtg_params,
 		.program_manual_trigger = optc2_program_manual_trigger,
 		.setup_manual_trigger = optc301_setup_manual_trigger,
 		.get_hw_timing = optc1_get_hw_timing,
 		.wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
 };

 void dcn301_timing_generator_init(struct optc *optc1)
 {
 	optc1->base.funcs = &dcn30_tg_funcs;

 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;

 	optc1->min_h_blank = 32;
 	optc1->min_v_blank = 3;
 	optc1->min_v_blank_interlace = 5;
 	optc1->min_h_sync_width = 4;
 	optc1->min_v_sync_width = 1;
 }
	/*
	* Copyright 2020 Advanced Micro Devices, Inc.
	*
	* Permission is hereby granted, free of charge, to any person obtaining a
	* copy of this software and associated documentation files (the "Software"),
	* to deal in the Software without restriction, including without limitation
	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	* and/or sell copies of the Software, and to permit persons to whom the
	* Software is furnished to do so, subject to the following conditions:
	*
	* The above copyright notice and this permission notice shall be included in
	* all copies or substantial portions of the Software.
	*
	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	* OTHER DEALINGS IN THE SOFTWARE.
	*
	* Authors: AMD
	*
	*/

	#include "reg_helper.h"
	#include "dcn301_optc.h"
	#include "dc.h"
	#include "dcn_calc_math.h"
	#include "dc_dmub_srv.h"

	#include "dml/dcn30/dcn30_fpu.h"
	#include "dc_trace.h"

	#define REG(reg)\
	optc1->tg_regs->reg

	#define CTX \
	optc1->base.ctx

	#undef FN
	#define FN(reg_name, field_name) \
	optc1->tg_shift->field_name, optc1->tg_mask->field_name


	/**
	* optc301_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
	*
	* @optc: timing_generator instance.
	* @params: parameters used for Dynamic Refresh Rate.
	*/
	void optc301_set_drr(
	struct timing_generator *optc,
	const struct drr_params *params)
	{
	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	if (params != NULL &&
	params->vertical_total_max > 0 &&
	params->vertical_total_min > 0) {

	if (params->vertical_total_mid != 0) {

	REG_SET(OTG_V_TOTAL_MID, 0,
	OTG_V_TOTAL_MID, params->vertical_total_mid - 1);

	REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
	OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
	OTG_VTOTAL_MID_FRAME_NUM,
	(uint8_t)params->vertical_total_mid_frame_num);

	}

	optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);

	REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
	OTG_V_TOTAL_MIN_SEL, 1,
	OTG_V_TOTAL_MAX_SEL, 1,
	OTG_FORCE_LOCK_ON_EVENT, 0,
	OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
	OTG_SET_V_TOTAL_MIN_MASK, 0);
	// Setup manual flow control for EOF via TRIG_A
	optc->funcs->setup_manual_trigger(optc);

	} else {
	REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
	OTG_SET_V_TOTAL_MIN_MASK, 0,
	OTG_V_TOTAL_MIN_SEL, 0,
	OTG_V_TOTAL_MAX_SEL, 0,
	OTG_FORCE_LOCK_ON_EVENT, 0);

	optc->funcs->set_vtotal_min_max(optc, 0, 0);
	}
	}


	void optc301_setup_manual_trigger(struct timing_generator *optc)
	{
	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	REG_SET_8(OTG_TRIGA_CNTL, 0,
	OTG_TRIGA_SOURCE_SELECT, 21,
	OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
	OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
	OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
	OTG_TRIGA_POLARITY_SELECT, 0,
	OTG_TRIGA_FREQUENCY_SELECT, 0,
	OTG_TRIGA_DELAY, 0,
	OTG_TRIGA_CLEAR, 1);
	}

	static struct timing_generator_funcs dcn30_tg_funcs = {
	.validate_timing = optc1_validate_timing,
	.program_timing = optc1_program_timing,
	.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
	.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
	.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
	.program_global_sync = optc1_program_global_sync,
	.enable_crtc = optc2_enable_crtc,
	.disable_crtc = optc1_disable_crtc,
	/* used by enable_timing_synchronization. Not need for FPGA */
	.is_counter_moving = optc1_is_counter_moving,
	.get_position = optc1_get_position,
	.get_frame_count = optc1_get_vblank_counter,
	.get_scanoutpos = optc1_get_crtc_scanoutpos,
	.get_otg_active_size = optc1_get_otg_active_size,
	.set_early_control = optc1_set_early_control,
	/* used by enable_timing_synchronization. Not need for FPGA */
	.wait_for_state = optc1_wait_for_state,
	.set_blank_color = optc3_program_blank_color,
	.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
	.triplebuffer_lock = optc3_triplebuffer_lock,
	.triplebuffer_unlock = optc2_triplebuffer_unlock,
	.enable_reset_trigger = optc1_enable_reset_trigger,
	.enable_crtc_reset = optc1_enable_crtc_reset,
	.disable_reset_trigger = optc1_disable_reset_trigger,
	.lock = optc3_lock,
	.unlock = optc1_unlock,
	.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
	.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
	.enable_optc_clock = optc1_enable_optc_clock,
	.set_drr = optc301_set_drr,
	.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
	.set_vtotal_min_max = optc3_set_vtotal_min_max,
	.set_static_screen_control = optc1_set_static_screen_control,
	.program_stereo = optc1_program_stereo,
	.is_stereo_left_eye = optc1_is_stereo_left_eye,
	.tg_init = optc3_tg_init,
	.is_tg_enabled = optc1_is_tg_enabled,
	.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
	.clear_optc_underflow = optc1_clear_optc_underflow,
	.setup_global_swap_lock = NULL,
	.get_crc = optc1_get_crc,
	.configure_crc = optc2_configure_crc,
	.set_dsc_config = optc3_set_dsc_config,
	.get_dsc_status = optc2_get_dsc_status,
	.set_dwb_source = NULL,
	.set_odm_bypass = optc3_set_odm_bypass,
	.set_odm_combine = optc3_set_odm_combine,
	.get_optc_source = optc2_get_optc_source,
	.set_out_mux = optc3_set_out_mux,
	.set_drr_trigger_window = optc3_set_drr_trigger_window,
	.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
	.set_gsl = optc2_set_gsl,
	.set_gsl_source_select = optc2_set_gsl_source_select,
	.set_vtg_params = optc1_set_vtg_params,
	.program_manual_trigger = optc2_program_manual_trigger,
	.setup_manual_trigger = optc301_setup_manual_trigger,
	.get_hw_timing = optc1_get_hw_timing,
	.wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
	};

	void dcn301_timing_generator_init(struct optc *optc1)
	{
	optc1->base.funcs = &dcn30_tg_funcs;

	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;

	optc1->min_h_blank = 32;
	optc1->min_v_blank = 3;
	optc1->min_v_blank_interlace = 5;
	optc1->min_h_sync_width = 4;
	optc1->min_v_sync_width = 1;
	}