| // SPDX-License-Identifier: GPL-2.0 OR X11 |
| /* |
| * Copyright (C) 2016 Boundary Devices, Inc. |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx6sx.dtsi" |
| |
| / { |
| model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; |
| compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x40000000>; |
| }; |
| |
| backlight-lvds { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm4 0 5000000>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| power-supply = <®_3p3v>; |
| }; |
| |
| reg_1p8v: regulator-1p8v { |
| compatible = "regulator-fixed"; |
| regulator-name = "1P8V"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "3P3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| reg_can1_3v3: regulator-can1-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "can1-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_can2_3v3: regulator-can2-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "can2-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_usb_otg1_vbus: regulator-usb-otg1-vbus { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg1_vbus>; |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_wlan: regulator-wlan { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_wlan>; |
| compatible = "regulator-fixed"; |
| clocks = <&clks IMX6SX_CLK_CKO>; |
| clock-names = "slow"; |
| regulator-name = "wlan-en"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| startup-delay-us = <70000>; |
| gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| sound { |
| compatible = "fsl,imx-audio-sgtl5000"; |
| model = "imx6sx-nitrogen6sx-sgtl5000"; |
| cpu-dai = <&ssi1>; |
| audio-codec = <&codec>; |
| audio-routing = |
| "MIC_IN", "Mic Jack", |
| "Mic Jack", "Mic Bias", |
| "Headphone Jack", "HP_OUT"; |
| mux-int-port = <1>; |
| mux-ext-port = <5>; |
| }; |
| }; |
| |
| &audmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_audmux>; |
| status = "okay"; |
| }; |
| |
| &ecspi1 { |
| cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi1>; |
| status = "okay"; |
| |
| flash: flash@0 { |
| compatible = "microchip,sst25vf016b"; |
| spi-max-frequency = <20000000>; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "U-Boot"; |
| reg = <0x0 0xc0000>; |
| read-only; |
| }; |
| |
| partition@c0000 { |
| label = "env"; |
| reg = <0xc0000 0x2000>; |
| read-only; |
| }; |
| |
| partition@c2000 { |
| label = "Kernel"; |
| reg = <0xc2000 0x11e000>; |
| }; |
| |
| partition@1e0000 { |
| label = "M4"; |
| reg = <0x1e0000 0x20000>; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy1>; |
| phy-supply = <®_3p3v>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy1: ethernet-phy@4 { |
| reg = <4>; |
| }; |
| |
| ethphy2: ethernet-phy@5 { |
| reg = <5>; |
| }; |
| }; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2>; |
| phy-mode = "rgmii"; |
| phy-handle = <ðphy2>; |
| phy-supply = <®_3p3v>; |
| fsl,magic-packet; |
| status = "okay"; |
| }; |
| |
| &flexcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| xceiver-supply = <®_can1_3v3>; |
| status = "okay"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_can2_3v3>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| codec: sgtl5000@a { |
| compatible = "fsl,sgtl5000"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sgtl5000>; |
| reg = <0x0a>; |
| clocks = <&clks IMX6SX_CLK_CKO2>; |
| VDDA-supply = <®_1p8v>; |
| VDDIO-supply = <®_1p8v>; |
| VDDD-supply = <®_1p8v>; |
| assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, |
| <&clks IMX6SX_CLK_CKO2>; |
| assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; |
| assigned-clock-rates = <0>, <24000000>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| status = "okay"; |
| }; |
| |
| &pcie { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie>; |
| reset-gpio = <&gpio4 10 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &pwm4 { |
| #pwm-cells = <2>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm4>; |
| status = "okay"; |
| }; |
| |
| &ssi1 { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &uart5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart5>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg1>; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg2>; |
| dr_mode = "host"; |
| disable-over-current; |
| reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| bus-width = <4>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| keep-power-in-suspend; |
| wakeup-source; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| bus-width = <4>; |
| non-removable; |
| keep-power-in-suspend; |
| vmmc-supply = <®_wlan>; |
| cap-power-off-card; |
| cap-sdio-irq; |
| status = "okay"; |
| |
| brcmf: wifi@1 { |
| reg = <1>; |
| compatible = "brcm,bcm4329-fmac"; |
| interrupt-parent = <&gpio7>; |
| interrupts = <7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| wlcore: wlcore@2 { |
| compatible = "ti,wl1271"; |
| reg = <2>; |
| interrupt-parent = <&gpio7>; |
| interrupts = <7 IRQ_TYPE_LEVEL_LOW>; |
| ref-clock-frequency = <38400000>; |
| }; |
| }; |
| |
| &usdhc4 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc4_50mhz>; |
| pinctrl-1 = <&pinctrl_usdhc4_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc4_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| vmmc-supply = <®_1p8v>; |
| keep-power-in-suspend; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| pinctrl_audmux: audmuxgrp { |
| fsl,pins = < |
| MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 |
| MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 |
| MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 |
| MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_ecspi1: ecspi1grp { |
| fsl,pins = < |
| MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 |
| MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 |
| MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 |
| MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 |
| >; |
| }; |
| |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 |
| MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 |
| MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 |
| MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 |
| MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 |
| MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 |
| MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 |
| MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 |
| MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 |
| MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 |
| MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 |
| MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 |
| MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 |
| MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 |
| MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 |
| MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 |
| MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 |
| >; |
| }; |
| |
| pinctrl_enet2: enet2grp { |
| fsl,pins = < |
| MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 |
| MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 |
| MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 |
| MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 |
| MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 |
| MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 |
| MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 |
| MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 |
| MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 |
| MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 |
| MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 |
| MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 |
| MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 |
| MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 |
| MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp { |
| fsl,pins = < |
| MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 |
| MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 |
| MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 |
| MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 |
| MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 |
| MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 |
| >; |
| }; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 |
| MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 |
| MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 |
| MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 |
| MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 |
| MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 |
| MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 |
| MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 |
| MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 |
| MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 |
| MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 |
| MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 |
| /* Test points */ |
| MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 |
| MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 |
| MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 |
| MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 |
| MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_pcie: pciegrp { |
| fsl,pins = < |
| MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 |
| MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 |
| MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 |
| >; |
| }; |
| |
| pinctrl_pwm4: pwm4grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 |
| >; |
| }; |
| |
| pinctrl_reg_wlan: reg-wlangrp { |
| fsl,pins = < |
| MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 |
| MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 |
| >; |
| }; |
| |
| pinctrl_sgtl5000: sgtl5000grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 |
| MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 |
| MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 |
| MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 |
| MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 |
| MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1 |
| MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart5: uart5grp { |
| fsl,pins = < |
| MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1 |
| MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1 |
| MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1 |
| MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usbotg1: usbotg1grp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 |
| MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 |
| >; |
| }; |
| |
| pinctrl_usbotg1_vbus: usbotg1-vbusgrp { |
| fsl,pins = < |
| MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_usbotg2: usbotg2grp { |
| fsl,pins = < |
| MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 |
| MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 |
| MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 |
| MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 |
| MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 |
| MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 |
| MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 |
| MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 |
| MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 |
| MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 |
| MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 |
| MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 |
| >; |
| }; |
| |
| pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { |
| fsl,pins = < |
| MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 |
| MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 |
| MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 |
| MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 |
| MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 |
| MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 |
| MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 |
| MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 |
| MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 |
| MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 |
| MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 |
| >; |
| }; |
| |
| pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { |
| fsl,pins = < |
| MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 |
| MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 |
| MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 |
| MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 |
| MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 |
| MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 |
| MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 |
| MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 |
| MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 |
| MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { |
| fsl,pins = < |
| MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 |
| MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 |
| MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 |
| MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 |
| MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 |
| MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 |
| MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 |
| MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 |
| MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 |
| MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 |
| >; |
| }; |
| }; |
