| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for NXP Layerscape-1028A family SoC. |
| * |
| * Copyright 2018 NXP |
| * |
| * Harninder Rai <harninder.rai@nxp.com> |
| * |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| compatible = "fsl,ls1028a"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| clocks = <&clockgen 1 0>; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_PW20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a72"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| clocks = <&clockgen 1 0>; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_PW20>; |
| #cooling-cells = <2>; |
| }; |
| |
| l2: l2-cache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| idle-states { |
| /* |
| * PSCI node is not added default, U-boot will add missing |
| * parts if it determines to use PSCI. |
| */ |
| entry-method = "arm,psci"; |
| |
| CPU_PW20: cpu-pw20 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "PW20"; |
| arm,psci-suspend-param = <0x0>; |
| entry-latency-us = <2000>; |
| exit-latency-us = <2000>; |
| min-residency-us = <6000>; |
| }; |
| }; |
| |
| sysclk: clock-sysclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| clock-output-names = "sysclk"; |
| }; |
| |
| osc_27m: clock-osc-27m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <27000000>; |
| clock-output-names = "phy_27m"; |
| }; |
| |
| dpclk: clock-controller@f1f0000 { |
| compatible = "fsl,ls1028a-plldig"; |
| reg = <0x0 0xf1f0000 0x0 0xffff>; |
| #clock-cells = <0>; |
| clocks = <&osc_27m>; |
| }; |
| |
| reboot { |
| compatible ="syscon-reboot"; |
| regmap = <&rst>; |
| offset = <0xb0>; |
| mask = <0x02>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a72-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gic: interrupt-controller@6000000 { |
| compatible= "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ |
| #interrupt-cells= <3>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| its: gic-its@6020000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ |
| }; |
| }; |
| |
| thermal-zones { |
| core-cluster { |
| polling-delay-passive = <1000>; |
| polling-delay = <5000>; |
| thermal-sensors = <&tmu 0>; |
| |
| trips { |
| core_cluster_alert: core-cluster-alert { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| core_cluster_crit: core-cluster-crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&core_cluster_alert>; |
| cooling-device = |
| <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| ddr: memory-controller@1080000 { |
| compatible = "fsl,qoriq-memory-controller"; |
| reg = <0x0 0x1080000 0x0 0x1000>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| big-endian; |
| }; |
| |
| dcfg: syscon@1e00000 { |
| compatible = "fsl,ls1028a-dcfg", "syscon"; |
| reg = <0x0 0x1e00000 0x0 0x10000>; |
| big-endian; |
| }; |
| |
| rst: syscon@1e60000 { |
| compatible = "syscon"; |
| reg = <0x0 0x1e60000 0x0 0x10000>; |
| little-endian; |
| }; |
| |
| scfg: syscon@1fc0000 { |
| compatible = "fsl,ls1028a-scfg", "syscon"; |
| reg = <0x0 0x1fc0000 0x0 0x10000>; |
| big-endian; |
| }; |
| |
| clockgen: clock-controller@1300000 { |
| compatible = "fsl,ls1028a-clockgen"; |
| reg = <0x0 0x1300000 0x0 0xa0000>; |
| #clock-cells = <2>; |
| clocks = <&sysclk>; |
| }; |
| |
| i2c0: i2c@2000000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2000000 0x0 0x10000>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@2010000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2010000 0x0 0x10000>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@2020000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2020000 0x0 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@2030000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2030000 0x0 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@2040000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2040000 0x0 0x10000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@2050000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2050000 0x0 0x10000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@2060000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2060000 0x0 0x10000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@2070000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2070000 0x0 0x10000>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| esdhc: mmc@2140000 { |
| compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x2140000 0x0 0x10000>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <0>; /* fixed up by bootloader */ |
| clocks = <&clockgen 2 1>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| little-endian; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| esdhc1: mmc@2150000 { |
| compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x2150000 0x0 0x10000>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <0>; /* fixed up by bootloader */ |
| clocks = <&clockgen 2 1>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| broken-cd; |
| little-endian; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| duart0: serial@21c0500 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x00 0x21c0500 0x0 0x100>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| duart1: serial@21c0600 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x00 0x21c0600 0x0 0x100>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| edma0: dma-controller@22c0000 { |
| #dma-cells = <2>; |
| compatible = "fsl,vf610-edma"; |
| reg = <0x0 0x22c0000 0x0 0x10000>, |
| <0x0 0x22d0000 0x0 0x10000>, |
| <0x0 0x22e0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma-tx", "edma-err"; |
| dma-channels = <32>; |
| clock-names = "dmamux0", "dmamux1"; |
| clocks = <&clockgen 4 1>, |
| <&clockgen 4 1>; |
| }; |
| |
| gpio1: gpio@2300000 { |
| compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; |
| reg = <0x0 0x2300000 0x0 0x10000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| little-endian; |
| }; |
| |
| gpio2: gpio@2310000 { |
| compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; |
| reg = <0x0 0x2310000 0x0 0x10000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| little-endian; |
| }; |
| |
| gpio3: gpio@2320000 { |
| compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; |
| reg = <0x0 0x2320000 0x0 0x10000>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| little-endian; |
| }; |
| |
| usb0: usb@3100000 { |
| compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; |
| reg = <0x0 0x3100000 0x0 0x10000>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| dr_mode = "host"; |
| snps,dis_rxdet_inp3_quirk; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
| }; |
| |
| usb1: usb@3110000 { |
| compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; |
| reg = <0x0 0x3110000 0x0 0x10000>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| dr_mode = "host"; |
| snps,dis_rxdet_inp3_quirk; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
| }; |
| |
| sata: sata@3200000 { |
| compatible = "fsl,ls1028a-ahci"; |
| reg = <0x0 0x3200000 0x0 0x10000>, |
| <0x7 0x100520 0x0 0x4>; |
| reg-names = "ahci", "sata-ecc"; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 1>; |
| status = "disabled"; |
| }; |
| |
| smmu: iommu@5000000 { |
| compatible = "arm,mmu-500"; |
| reg = <0 0x5000000 0 0x800000>; |
| #global-interrupts = <8>; |
| #iommu-cells = <1>; |
| stream-match-mask = <0x7c00>; |
| /* global secure fault */ |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| /* combined secure interrupt */ |
| <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| /* global non-secure fault */ |
| <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| /* combined non-secure interrupt */ |
| <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| /* performance counter interrupts 0-7 */ |
| <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| /* per context interrupt, 64 interrupts */ |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| crypto: crypto@8000000 { |
| compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; |
| fsl,sec-era = <10>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x8000000 0x100000>; |
| reg = <0x00 0x8000000 0x0 0x100000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| dma-coherent; |
| |
| sec_jr0: jr@10000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr1: jr@20000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x20000 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr2: jr@30000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x30000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr3: jr@40000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x40000 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| qdma: dma-controller@8380000 { |
| compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; |
| reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ |
| <0x0 0x8390000 0x0 0x10000>, /* Status regs */ |
| <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "qdma-error", "qdma-queue0", |
| "qdma-queue1", "qdma-queue2", "qdma-queue3"; |
| dma-channels = <8>; |
| block-number = <1>; |
| block-offset = <0x10000>; |
| fsl,dma-queues = <2>; |
| status-sizes = <64>; |
| queue-sizes = <64 64>; |
| }; |
| |
| cluster1_core0_watchdog: watchdog@c000000 { |
| compatible = "arm,sp805", "arm,primecell"; |
| reg = <0x0 0xc000000 0x0 0x1000>; |
| clocks = <&clockgen 4 15>, <&clockgen 4 15>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster1_core1_watchdog: watchdog@c010000 { |
| compatible = "arm,sp805", "arm,primecell"; |
| reg = <0x0 0xc010000 0x0 0x1000>; |
| clocks = <&clockgen 4 15>, <&clockgen 4 15>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| sai1: audio-controller@f100000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf100000 0x0 0x10000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&clockgen 4 1>, <&clockgen 4 1>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 4>, |
| <&edma0 1 3>; |
| status = "disabled"; |
| }; |
| |
| sai2: audio-controller@f110000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf110000 0x0 0x10000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&clockgen 4 1>, <&clockgen 4 1>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 6>, |
| <&edma0 1 5>; |
| status = "disabled"; |
| }; |
| |
| sai4: audio-controller@f130000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,vf610-sai"; |
| reg = <0x0 0xf130000 0x0 0x10000>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 1>, <&clockgen 4 1>, |
| <&clockgen 4 1>, <&clockgen 4 1>; |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
| dma-names = "tx", "rx"; |
| dmas = <&edma0 1 10>, |
| <&edma0 1 9>; |
| status = "disabled"; |
| }; |
| |
| tmu: tmu@1f80000 { |
| compatible = "fsl,qoriq-tmu"; |
| reg = <0x0 0x1f80000 0x0 0x10000>; |
| interrupts = <0 23 0x4>; |
| fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; |
| fsl,tmu-calibration = <0x00000000 0x00000024 |
| 0x00000001 0x0000002b |
| 0x00000002 0x00000031 |
| 0x00000003 0x00000038 |
| 0x00000004 0x0000003f |
| 0x00000005 0x00000045 |
| 0x00000006 0x0000004c |
| 0x00000007 0x00000053 |
| 0x00000008 0x00000059 |
| 0x00000009 0x00000060 |
| 0x0000000a 0x00000066 |
| 0x0000000b 0x0000006d |
| |
| 0x00010000 0x0000001c |
| 0x00010001 0x00000024 |
| 0x00010002 0x0000002c |
| 0x00010003 0x00000035 |
| 0x00010004 0x0000003d |
| 0x00010005 0x00000045 |
| 0x00010006 0x0000004d |
| 0x00010007 0x00000055 |
| 0x00010008 0x0000005e |
| 0x00010009 0x00000066 |
| 0x0001000a 0x0000006e |
| |
| 0x00020000 0x00000018 |
| 0x00020001 0x00000022 |
| 0x00020002 0x0000002d |
| 0x00020003 0x00000038 |
| 0x00020004 0x00000043 |
| 0x00020005 0x0000004d |
| 0x00020006 0x00000058 |
| 0x00020007 0x00000063 |
| 0x00020008 0x0000006e |
| |
| 0x00030000 0x00000010 |
| 0x00030001 0x0000001c |
| 0x00030002 0x00000029 |
| 0x00030003 0x00000036 |
| 0x00030004 0x00000042 |
| 0x00030005 0x0000004f |
| 0x00030006 0x0000005b |
| 0x00030007 0x00000068>; |
| little-endian; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| pcie@1f0000000 { /* Integrated Endpoint Root Complex */ |
| compatible = "pci-host-ecam-generic"; |
| reg = <0x01 0xf0000000 0x0 0x100000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| msi-parent = <&its>; |
| device_type = "pci"; |
| bus-range = <0x0 0x0>; |
| dma-coherent; |
| msi-map = <0 &its 0x17 0xe>; |
| iommu-map = <0 &smmu 0x17 0xe>; |
| /* PF0-6 BAR0 - non-prefetchable memory */ |
| ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 |
| /* PF0-6 BAR2 - prefetchable memory */ |
| 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 |
| /* PF0: VF0-1 BAR0 - non-prefetchable memory */ |
| 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 |
| /* PF0: VF0-1 BAR2 - prefetchable memory */ |
| 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 |
| /* PF1: VF0-1 BAR0 - non-prefetchable memory */ |
| 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 |
| /* PF1: VF0-1 BAR2 - prefetchable memory */ |
| 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; |
| |
| enetc_port0: ethernet@0,0 { |
| compatible = "fsl,enetc"; |
| reg = <0x000000 0 0 0 0>; |
| }; |
| enetc_port1: ethernet@0,1 { |
| compatible = "fsl,enetc"; |
| reg = <0x000100 0 0 0 0>; |
| }; |
| enetc_mdio_pf3: mdio@0,3 { |
| compatible = "fsl,enetc-mdio"; |
| reg = <0x000300 0 0 0 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| ethernet@0,4 { |
| compatible = "fsl,enetc-ptp"; |
| reg = <0x000400 0 0 0 0>; |
| clocks = <&clockgen 4 0>; |
| little-endian; |
| }; |
| }; |
| }; |
| |
| malidp0: display@f080000 { |
| compatible = "arm,mali-dp500"; |
| reg = <0x0 0xf080000 0x0 0x10000>; |
| interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, |
| <0 223 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "DE", "SE"; |
| clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, |
| <&clockgen 2 2>; |
| clock-names = "pxlclk", "mclk", "aclk", "pclk"; |
| arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; |
| arm,malidp-arqos-value = <0xd000d000>; |
| |
| port { |
| dp0_out: endpoint { |
| |
| }; |
| }; |
| }; |
| }; |
