| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * sc7280 SoC device tree source |
| * |
| * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-sc7280.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/interconnect/qcom,sc7280.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/mailbox/qcom-ipcc.h> |
| #include <dt-bindings/power/qcom-aoss-qmp.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/reset/qcom,sdm845-aoss.h> |
| #include <dt-bindings/reset/qcom,sdm845-pdc.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| clock-frequency = <76800000>; |
| #clock-cells = <0>; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32000>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| aop_mem: memory@80800000 { |
| reg = <0x0 0x80800000 0x0 0x60000>; |
| no-map; |
| }; |
| |
| aop_cmd_db_mem: memory@80860000 { |
| reg = <0x0 0x80860000 0x0 0x20000>; |
| compatible = "qcom,cmd-db"; |
| no-map; |
| }; |
| |
| smem_mem: memory@80900000 { |
| reg = <0x0 0x80900000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| cpucp_mem: memory@80b00000 { |
| no-map; |
| reg = <0x0 0x80b00000 0x0 0x100000>; |
| }; |
| |
| ipa_fw_mem: memory@8b700000 { |
| reg = <0 0x8b700000 0 0x10000>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_0>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "cache"; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_100>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| L2_100: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_200>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| L2_200: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
| &LITTLE_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_300>; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| L2_300: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_400>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| L2_400: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_500>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| L2_500: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_600>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| L2_600: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,kryo"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| cpu-idle-states = <&BIG_CPU_SLEEP_0 |
| &BIG_CPU_SLEEP_1 |
| &CLUSTER_SLEEP_0>; |
| next-level-cache = <&L2_700>; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| L2_700: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "little-power-down"; |
| arm,psci-suspend-param = <0x40000003>; |
| entry-latency-us = <549>; |
| exit-latency-us = <901>; |
| min-residency-us = <1774>; |
| local-timer-stop; |
| }; |
| |
| LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "little-rail-power-down"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <702>; |
| exit-latency-us = <915>; |
| min-residency-us = <4001>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "big-power-down"; |
| arm,psci-suspend-param = <0x40000003>; |
| entry-latency-us = <523>; |
| exit-latency-us = <1244>; |
| min-residency-us = <2207>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_1: cpu-sleep-1-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "big-rail-power-down"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <526>; |
| exit-latency-us = <1854>; |
| min-residency-us = <5555>; |
| local-timer-stop; |
| }; |
| |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "cluster-power-down"; |
| arm,psci-suspend-param = <0x40003444>; |
| entry-latency-us = <3263>; |
| exit-latency-us = <6562>; |
| min-residency-us = <9926>; |
| local-timer-stop; |
| }; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0 0x80000000 0 0>; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-sc7280", "qcom,scm"; |
| }; |
| }; |
| |
| clk_virt: interconnect { |
| compatible = "qcom,sc7280-clk-virt"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| smp2p-adsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| adsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| adsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-cdsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| cdsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| cdsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-mpss { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_MPSS |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_MPSS |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| ipa_smp2p_out: ipa-ap-to-modem { |
| qcom,entry-name = "ipa"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| ipa_smp2p_in: ipa-modem-to-ap { |
| qcom,entry-name = "ipa"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-wpss { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <617>, <616>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_WPSS |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_WPSS |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <13>; |
| |
| wpss_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| wpss_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc: soc@0 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sc7280"; |
| reg = <0 0x00100000 0 0x1f0000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, |
| <0>, <0>, <0>, <0>, <0>, <0>; |
| clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", |
| "pcie_0_pipe_clk", "pcie_1_pipe-clk", |
| "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", |
| "ufs_phy_tx_symbol_0_clk", |
| "usb3_phy_wrapper_gcc_usb30_pipe_clk"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| ipcc: mailbox@408000 { |
| compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; |
| reg = <0 0x00408000 0 0x1000>; |
| interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #mbox-cells = <2>; |
| }; |
| |
| qupv3_id_0: geniqup@9c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x009c0000 0 0x2000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| uart5: serial@994000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0 0x00994000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| cnoc2: interconnect@1500000 { |
| reg = <0 0x01500000 0 0x1000>; |
| compatible = "qcom,sc7280-cnoc2"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| cnoc3: interconnect@1502000 { |
| reg = <0 0x01502000 0 0x1000>; |
| compatible = "qcom,sc7280-cnoc3"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mc_virt: interconnect@1580000 { |
| reg = <0 0x01580000 0 0x4>; |
| compatible = "qcom,sc7280-mc-virt"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| system_noc: interconnect@1680000 { |
| reg = <0 0x01680000 0 0x15480>; |
| compatible = "qcom,sc7280-system-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre1_noc: interconnect@16e0000 { |
| compatible = "qcom,sc7280-aggre1-noc"; |
| reg = <0 0x016e0000 0 0x1c080>; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre2_noc: interconnect@1700000 { |
| reg = <0 0x01700000 0 0x2b080>; |
| compatible = "qcom,sc7280-aggre2-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mmss_noc: interconnect@1740000 { |
| reg = <0 0x01740000 0 0x1e080>; |
| compatible = "qcom,sc7280-mmss-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| ipa: ipa@1e40000 { |
| compatible = "qcom,sc7280-ipa"; |
| |
| iommus = <&apps_smmu 0x480 0x0>, |
| <&apps_smmu 0x482 0x0>; |
| reg = <0 0x1e40000 0 0x8000>, |
| <0 0x1e50000 0 0x4ad0>, |
| <0 0x1e04000 0 0x23000>; |
| reg-names = "ipa-reg", |
| "ipa-shared", |
| "gsi"; |
| |
| interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, |
| <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, |
| <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "ipa", |
| "gsi", |
| "ipa-clock-query", |
| "ipa-setup-ready"; |
| |
| clocks = <&rpmhcc RPMH_IPA_CLK>; |
| clock-names = "core"; |
| |
| interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; |
| interconnect-names = "memory", |
| "config"; |
| |
| qcom,smem-states = <&ipa_smp2p_out 0>, |
| <&ipa_smp2p_out 1>; |
| qcom,smem-state-names = "ipa-clock-enabled-valid", |
| "ipa-clock-enabled"; |
| |
| status = "disabled"; |
| }; |
| |
| tcsr_mutex: hwlock@1f40000 { |
| compatible = "qcom,tcsr-mutex", "syscon"; |
| reg = <0 0x01f40000 0 0x40000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| lpasscc: lpasscc@3000000 { |
| compatible = "qcom,sc7280-lpasscc"; |
| reg = <0 0x03000000 0 0x40>, |
| <0 0x03c04000 0 0x4>, |
| <0 0x03389000 0 0x24>; |
| reg-names = "qdsp6ss", "top_cc", "cc"; |
| clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; |
| clock-names = "iface"; |
| #clock-cells = <1>; |
| }; |
| |
| lpass_ag_noc: interconnect@3c40000 { |
| reg = <0 0x03c40000 0 0xf080>; |
| compatible = "qcom,sc7280-lpass-ag-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| gpucc: clock-controller@3d90000 { |
| compatible = "qcom,sc7280-gpucc"; |
| reg = <0 0x03d90000 0 0x9000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_GPU_GPLL0_CLK_SRC>, |
| <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
| clock-names = "bi_tcxo", |
| "gcc_gpu_gpll0_clk_src", |
| "gcc_gpu_gpll0_div_clk_src"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| stm@6002000 { |
| compatible = "arm,coresight-stm", "arm,primecell"; |
| reg = <0 0x06002000 0 0x1000>, |
| <0 0x16280000 0 0x180000>; |
| reg-names = "stm-base", "stm-stimulus-base"; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| stm_out: endpoint { |
| remote-endpoint = <&funnel0_in7>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6041000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06041000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel0_out: endpoint { |
| remote-endpoint = <&merge_funnel_in0>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@7 { |
| reg = <7>; |
| funnel0_in7: endpoint { |
| remote-endpoint = <&stm_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6042000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06042000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel1_out: endpoint { |
| remote-endpoint = <&merge_funnel_in1>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@4 { |
| reg = <4>; |
| funnel1_in4: endpoint { |
| remote-endpoint = <&apss_merge_funnel_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6045000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06045000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| merge_funnel_out: endpoint { |
| remote-endpoint = <&swao_funnel_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| merge_funnel_in0: endpoint { |
| remote-endpoint = <&funnel0_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| merge_funnel_in1: endpoint { |
| remote-endpoint = <&funnel1_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| replicator@6046000 { |
| compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
| reg = <0 0x06046000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| replicator_out: endpoint { |
| remote-endpoint = <&etr_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| replicator_in: endpoint { |
| remote-endpoint = <&swao_replicator_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etr@6048000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x06048000 0 0x1000>; |
| iommus = <&apps_smmu 0x04c0 0>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,scatter-gather; |
| |
| in-ports { |
| port { |
| etr_in: endpoint { |
| remote-endpoint = <&replicator_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@6b04000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x06b04000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| swao_funnel_out: endpoint { |
| remote-endpoint = <&etf_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@7 { |
| reg = <7>; |
| swao_funnel_in: endpoint { |
| remote-endpoint = <&merge_funnel_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etf@6b05000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x06b05000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etf_out: endpoint { |
| remote-endpoint = <&swao_replicator_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| etf_in: endpoint { |
| remote-endpoint = <&swao_funnel_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| replicator@6b06000 { |
| compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
| reg = <0 0x06b06000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| qcom,replicator-loses-context; |
| |
| out-ports { |
| port { |
| swao_replicator_out: endpoint { |
| remote-endpoint = <&replicator_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| swao_replicator_in: endpoint { |
| remote-endpoint = <&etf_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7040000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07040000 0 0x1000>; |
| |
| cpu = <&CPU0>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm0_out: endpoint { |
| remote-endpoint = <&apss_funnel_in0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7140000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07140000 0 0x1000>; |
| |
| cpu = <&CPU1>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm1_out: endpoint { |
| remote-endpoint = <&apss_funnel_in1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7240000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07240000 0 0x1000>; |
| |
| cpu = <&CPU2>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm2_out: endpoint { |
| remote-endpoint = <&apss_funnel_in2>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7340000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07340000 0 0x1000>; |
| |
| cpu = <&CPU3>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm3_out: endpoint { |
| remote-endpoint = <&apss_funnel_in3>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7440000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07440000 0 0x1000>; |
| |
| cpu = <&CPU4>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm4_out: endpoint { |
| remote-endpoint = <&apss_funnel_in4>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7540000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07540000 0 0x1000>; |
| |
| cpu = <&CPU5>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm5_out: endpoint { |
| remote-endpoint = <&apss_funnel_in5>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7640000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07640000 0 0x1000>; |
| |
| cpu = <&CPU6>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm6_out: endpoint { |
| remote-endpoint = <&apss_funnel_in6>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@7740000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x07740000 0 0x1000>; |
| |
| cpu = <&CPU7>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| arm,coresight-loses-context-with-cpu; |
| qcom,skip-power-up; |
| |
| out-ports { |
| port { |
| etm7_out: endpoint { |
| remote-endpoint = <&apss_funnel_in7>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@7800000 { /* APSS Funnel */ |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x07800000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| apss_funnel_out: endpoint { |
| remote-endpoint = <&apss_merge_funnel_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| apss_funnel_in0: endpoint { |
| remote-endpoint = <&etm0_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| apss_funnel_in1: endpoint { |
| remote-endpoint = <&etm1_out>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| apss_funnel_in2: endpoint { |
| remote-endpoint = <&etm2_out>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| apss_funnel_in3: endpoint { |
| remote-endpoint = <&etm3_out>; |
| }; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| apss_funnel_in4: endpoint { |
| remote-endpoint = <&etm4_out>; |
| }; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| apss_funnel_in5: endpoint { |
| remote-endpoint = <&etm5_out>; |
| }; |
| }; |
| |
| port@6 { |
| reg = <6>; |
| apss_funnel_in6: endpoint { |
| remote-endpoint = <&etm6_out>; |
| }; |
| }; |
| |
| port@7 { |
| reg = <7>; |
| apss_funnel_in7: endpoint { |
| remote-endpoint = <&etm7_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@7810000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x07810000 0 0x1000>; |
| |
| clocks = <&aoss_qmp>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| apss_merge_funnel_out: endpoint { |
| remote-endpoint = <&funnel1_in4>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| apss_merge_funnel_in: endpoint { |
| remote-endpoint = <&apss_funnel_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| dc_noc: interconnect@90e0000 { |
| reg = <0 0x090e0000 0 0x5080>; |
| compatible = "qcom,sc7280-dc-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| gem_noc: interconnect@9100000 { |
| reg = <0 0x9100000 0 0xe2200>; |
| compatible = "qcom,sc7280-gem-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| system-cache-controller@9200000 { |
| compatible = "qcom,sc7280-llcc"; |
| reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; |
| reg-names = "llcc_base", "llcc_broadcast_base"; |
| interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| nsp_noc: interconnect@a0c0000 { |
| reg = <0 0x0a0c0000 0 0x10000>; |
| compatible = "qcom,sc7280-nsp-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| videocc: clock-controller@aaf0000 { |
| compatible = "qcom,sc7280-videocc"; |
| reg = <0 0xaaf0000 0 0x10000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>; |
| clock-names = "bi_tcxo", "bi_tcxo_ao"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| dispcc: clock-controller@af00000 { |
| compatible = "qcom,sc7280-dispcc"; |
| reg = <0 0xaf00000 0 0x20000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_DISP_GPLL0_CLK_SRC>, |
| <0>, <0>, <0>, <0>, <0>, <0>; |
| clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", |
| "dsi0_phy_pll_out_byteclk", |
| "dsi0_phy_pll_out_dsiclk", |
| "dp_phy_pll_link_clk", |
| "dp_phy_pll_vco_div_clk", |
| "edp_phy_pll_link_clk", |
| "edp_phy_pll_vco_div_clk"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| pdc: interrupt-controller@b220000 { |
| compatible = "qcom,sc7280-pdc", "qcom,pdc"; |
| reg = <0 0x0b220000 0 0x30000>; |
| qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, |
| <55 306 4>, <59 312 3>, <62 374 2>, |
| <64 434 2>, <66 438 3>, <69 86 1>, |
| <70 520 54>, <124 609 31>, <155 63 1>, |
| <156 716 12>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| pdc_reset: reset-controller@b5e0000 { |
| compatible = "qcom,sc7280-pdc-global"; |
| reg = <0 0x0b5e0000 0 0x20000>; |
| #reset-cells = <1>; |
| }; |
| |
| tsens0: thermal-sensor@c263000 { |
| compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; |
| reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
| <0 0x0c222000 0 0x1ff>; /* SROT */ |
| #qcom,sensors = <15>; |
| interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uplow","critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tsens1: thermal-sensor@c265000 { |
| compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; |
| reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
| <0 0x0c223000 0 0x1ff>; /* SROT */ |
| #qcom,sensors = <12>; |
| interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uplow","critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| aoss_reset: reset-controller@c2a0000 { |
| compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; |
| reg = <0 0x0c2a0000 0 0x31000>; |
| #reset-cells = <1>; |
| }; |
| |
| aoss_qmp: power-controller@c300000 { |
| compatible = "qcom,sc7280-aoss-qmp"; |
| reg = <0 0x0c300000 0 0x100000>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_AOP |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_AOP |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| |
| #clock-cells = <0>; |
| #power-domain-cells = <1>; |
| }; |
| |
| spmi_bus: spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0 0x0c440000 0 0x1100>, |
| <0 0x0c600000 0 0x2000000>, |
| <0 0x0e600000 0 0x100000>, |
| <0 0x0e700000 0 0xa0000>, |
| <0 0x0c40a000 0 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| tlmm: pinctrl@f100000 { |
| compatible = "qcom,sc7280-pinctrl"; |
| reg = <0 0x0f100000 0 0x300000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 175>; |
| wakeup-parent = <&pdc>; |
| |
| qup_uart5_default: qup-uart5-default { |
| pins = "gpio46", "gpio47"; |
| function = "qup13"; |
| }; |
| }; |
| |
| apps_smmu: iommu@15000000 { |
| compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; |
| reg = <0 0x15000000 0 0x100000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <1>; |
| dma-coherent; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0 0x17a00000 0 0x10000>, /* GICD */ |
| <0 0x17a60000 0 0x100000>; /* GICR * 8 */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
| |
| gic-its@17a40000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| #msi-cells = <1>; |
| reg = <0 0x17a40000 0 0x20000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| watchdog@17c10000 { |
| compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; |
| reg = <0 0x17c10000 0 0x1000>; |
| clocks = <&sleep_clk>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer@17c20000 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0 0x17c20000 0 0x1000>; |
| |
| frame@17c21000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c21000 0 0x1000>, |
| <0 0x17c22000 0 0x1000>; |
| }; |
| |
| frame@17c23000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c23000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c25000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c25000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c27000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c27000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c29000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c29000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2b000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c2b000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2d000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17c2d000 0 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| apps_rsc: rsc@18200000 { |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0 0x18200000 0 0x10000>, |
| <0 0x18210000 0 0x10000>, |
| <0 0x18220000 0 0x10000>; |
| reg-names = "drv-0", "drv-1", "drv-2"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, |
| <CONTROL_TCS 1>; |
| |
| apps_bcm_voter: bcm-voter { |
| compatible = "qcom,bcm-voter"; |
| }; |
| |
| rpmhpd: power-controller { |
| compatible = "qcom,sc7280-rpmhpd"; |
| #power-domain-cells = <1>; |
| operating-points-v2 = <&rpmhpd_opp_table>; |
| |
| rpmhpd_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| rpmhpd_opp_ret: opp1 { |
| opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| }; |
| |
| rpmhpd_opp_low_svs: opp2 { |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| }; |
| |
| rpmhpd_opp_svs: opp3 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| |
| rpmhpd_opp_svs_l1: opp4 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| |
| rpmhpd_opp_svs_l2: opp5 { |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; |
| }; |
| |
| rpmhpd_opp_nom: opp6 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| rpmhpd_opp_nom_l1: opp7 { |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| rpmhpd_opp_turbo: opp8 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| }; |
| |
| rpmhpd_opp_turbo_l1: opp9 { |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| }; |
| }; |
| }; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sc7280-rpmh-clk"; |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| cpufreq_hw: cpufreq@18591000 { |
| compatible = "qcom,cpufreq-epss"; |
| reg = <0 0x18591000 0 0x1000>, |
| <0 0x18592000 0 0x1000>, |
| <0 0x18593000 0 0x1000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; |
| clock-names = "xo", "alternate"; |
| #freq-domain-cells = <1>; |
| }; |
| }; |
| |
| thermal_zones: thermal-zones { |
| cpu0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 1>; |
| |
| trips { |
| cpu0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu0_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu0_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu0_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu0_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 2>; |
| |
| trips { |
| cpu1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu1_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu1_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu1_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu1_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu2-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 3>; |
| |
| trips { |
| cpu2_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu2_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu2_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu2_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu2_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu3-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 4>; |
| |
| trips { |
| cpu3_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu3_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu3_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu3_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu3_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu4-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 7>; |
| |
| trips { |
| cpu4_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu4_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu4_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu5-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 8>; |
| |
| trips { |
| cpu5_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu5_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu5_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu6-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 9>; |
| |
| trips { |
| cpu6_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu6_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu6_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu7-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 10>; |
| |
| trips { |
| cpu7_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu7_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu7_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu8-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 11>; |
| |
| trips { |
| cpu8_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu8_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu8_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu8_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu8_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu9-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 12>; |
| |
| trips { |
| cpu9_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu9_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu9_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu9_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu9_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu10-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 13>; |
| |
| trips { |
| cpu10_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu10_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu10_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu10_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu10_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu11-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 14>; |
| |
| trips { |
| cpu11_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu11_alert1: trip-point1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu11_crit: cpu-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu11_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu11_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| aoss0-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 0>; |
| |
| trips { |
| aoss0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| aoss0_crit: aoss0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| aoss1-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 0>; |
| |
| trips { |
| aoss1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| aoss1_crit: aoss1-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpuss0-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 5>; |
| |
| trips { |
| cpuss0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| cpuss0_crit: cluster0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| cpuss1-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens0 6>; |
| |
| trips { |
| cpuss1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| cpuss1_crit: cluster0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| gpuss0-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 1>; |
| |
| trips { |
| gpuss0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| gpuss0_crit: gpuss0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| gpuss1-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 2>; |
| |
| trips { |
| gpuss1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| gpuss1_crit: gpuss1-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| nspss0-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 3>; |
| |
| trips { |
| nspss0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| nspss0_crit: nspss0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| nspss1-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 4>; |
| |
| trips { |
| nspss1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| nspss1_crit: nspss1-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| video-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 5>; |
| |
| trips { |
| video_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| video_crit: video-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| ddr-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 6>; |
| |
| trips { |
| ddr_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| ddr_crit: ddr-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| mdmss0-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 7>; |
| |
| trips { |
| mdmss0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| mdmss0_crit: mdmss0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| mdmss1-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 8>; |
| |
| trips { |
| mdmss1_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| mdmss1_crit: mdmss1-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| mdmss2-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 9>; |
| |
| trips { |
| mdmss2_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| mdmss2_crit: mdmss2-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| mdmss3-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 10>; |
| |
| trips { |
| mdmss3_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| mdmss3_crit: mdmss3-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| |
| camera0-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| |
| thermal-sensors = <&tsens1 11>; |
| |
| trips { |
| camera0_alert0: trip-point0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "hot"; |
| }; |
| |
| camera0_crit: camera0-crit { |
| temperature = <110000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
