| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Device Tree Source for the R-Car E3 (R8A77990) SoC |
| * |
| * Copyright (C) 2018 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/clock/r8a77990-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a77990-sysc.h> |
| |
| / { |
| compatible = "renesas,r8a77990"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| i2c7 = &i2c7; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| a53_0: cpu@0 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A77990_PD_CA53_CPU0>; |
| next-level-cache = <&L2_CA53>; |
| enable-method = "psci"; |
| }; |
| |
| a53_1: cpu@1 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <1>; |
| device_type = "cpu"; |
| power-domains = <&sysc R8A77990_PD_CA53_CPU1>; |
| next-level-cache = <&L2_CA53>; |
| enable-method = "psci"; |
| }; |
| |
| L2_CA53: cache-controller-0 { |
| compatible = "cache"; |
| power-domains = <&sysc R8A77990_PD_CA53_SCU>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| }; |
| |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| pmu_a53 { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, |
| <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&a53_0>, <&a53_1>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| /* External SCIF clock - to be overridden by boards that provide it */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| rwdt: watchdog@e6020000 { |
| compatible = "renesas,r8a77990-wdt", |
| "renesas,rcar-gen3-wdt"; |
| reg = <0 0xe6020000 0 0x0c>; |
| clocks = <&cpg CPG_MOD 402>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 402>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@e6050000 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6050000 0 0x50>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 18>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 912>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 912>; |
| }; |
| |
| gpio1: gpio@e6051000 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6051000 0 0x50>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 23>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 911>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 911>; |
| }; |
| |
| gpio2: gpio@e6052000 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6052000 0 0x50>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 26>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 910>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 910>; |
| }; |
| |
| gpio3: gpio@e6053000 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6053000 0 0x50>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 909>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 909>; |
| }; |
| |
| gpio4: gpio@e6054000 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6054000 0 0x50>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 11>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 908>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 908>; |
| }; |
| |
| gpio5: gpio@e6055000 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055000 0 0x50>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 20>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 907>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 907>; |
| }; |
| |
| gpio6: gpio@e6055400 { |
| compatible = "renesas,gpio-r8a77990", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055400 0 0x50>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 192 18>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 906>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 906>; |
| }; |
| |
| i2c0: i2c@e6500000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6500000 0 0x40>; |
| interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 931>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 931>; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@e6508000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6508000 0 0x40>; |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 930>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 930>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@e6510000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6510000 0 0x40>; |
| interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 929>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 929>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@e66d0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66d0000 0 0x40>; |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 928>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 928>; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@e66d8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66d8000 0 0x40>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 927>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 927>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@e66e0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66e0000 0 0x40>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 919>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 919>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@e66e8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66e8000 0 0x40>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 918>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 918>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@e6690000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a77990", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6690000 0 0x40>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 1003>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 1003>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| pfc: pin-controller@e6060000 { |
| compatible = "renesas,pfc-r8a77990"; |
| reg = <0 0xe6060000 0 0x508>; |
| }; |
| |
| cpg: clock-controller@e6150000 { |
| compatible = "renesas,r8a77990-cpg-mssr"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>; |
| clock-names = "extal"; |
| #clock-cells = <2>; |
| #power-domain-cells = <0>; |
| #reset-cells = <1>; |
| }; |
| |
| rst: reset-controller@e6160000 { |
| compatible = "renesas,r8a77990-rst"; |
| reg = <0 0xe6160000 0 0x0200>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a77990-sysc"; |
| reg = <0 0xe6180000 0 0x0400>; |
| #power-domain-cells = <1>; |
| }; |
| |
| dmac0: dma-controller@e6700000 { |
| compatible = "renesas,dmac-r8a77990", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6700000 0 0x10000>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 219>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 219>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, |
| <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, |
| <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, |
| <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, |
| <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, |
| <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, |
| <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; |
| }; |
| |
| dmac1: dma-controller@e7300000 { |
| compatible = "renesas,dmac-r8a77990", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7300000 0 0x10000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 218>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 218>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, |
| <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, |
| <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, |
| <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, |
| <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, |
| <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, |
| <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; |
| }; |
| |
| dmac2: dma-controller@e7310000 { |
| compatible = "renesas,dmac-r8a77990", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7310000 0 0x10000>; |
| interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 217>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 217>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, |
| <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, |
| <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, |
| <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, |
| <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, |
| <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, |
| <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; |
| }; |
| |
| ipmmu_ds0: mmu@e6740000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xe6740000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 0>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_ds1: mmu@e7740000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xe7740000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 1>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_hc: mmu@e6570000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xe6570000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 2>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_mm: mmu@e67b0000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xe67b0000 0 0x1000>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_mp: mmu@ec670000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xec670000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 4>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_pv0: mmu@fd800000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xfd800000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 6>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_rt: mmu@ffc80000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xffc80000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 10>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vc0: mmu@fe6b0000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xfe6b0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 12>; |
| power-domains = <&sysc R8A77990_PD_A3VC>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vi0: mmu@febd0000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xfebd0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 14>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vp0: mmu@fe990000 { |
| compatible = "renesas,ipmmu-r8a77990"; |
| reg = <0 0xfe990000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 16>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| avb: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a77990", |
| "renesas,etheravb-rcar-gen3"; |
| reg = <0 0xe6800000 0 0x800>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 812>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 812>; |
| phy-mode = "rgmii"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@e6e30000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e30000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@e6e31000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e31000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm2: pwm@e6e32000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e32000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm3: pwm@e6e33000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e33000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm4: pwm@e6e34000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e34000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm5: pwm@e6e35000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e35000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm6: pwm@e6e36000 { |
| compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; |
| reg = <0 0xe6e36000 0 0x8>; |
| clocks = <&cpg CPG_MOD 523>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 523>; |
| #pwm-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| scif2: serial@e6e88000 { |
| compatible = "renesas,scif-r8a77990", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e88000 0 64>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 310>, |
| <&cpg CPG_CORE R8A77990_CLK_S3D1C>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 310>; |
| status = "disabled"; |
| }; |
| |
| msiof0: spi@e6e90000 { |
| compatible = "renesas,msiof-r8a77990", |
| "renesas,rcar-gen3-msiof"; |
| reg = <0 0xe6e90000 0 0x0064>; |
| interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 211>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 211>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| msiof1: spi@e6ea0000 { |
| compatible = "renesas,msiof-r8a77990", |
| "renesas,rcar-gen3-msiof"; |
| reg = <0 0xe6ea0000 0 0x0064>; |
| interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 210>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 210>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| msiof2: spi@e6c00000 { |
| compatible = "renesas,msiof-r8a77990", |
| "renesas,rcar-gen3-msiof"; |
| reg = <0 0xe6c00000 0 0x0064>; |
| interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 209>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 209>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| msiof3: spi@e6c10000 { |
| compatible = "renesas,msiof-r8a77990", |
| "renesas,rcar-gen3-msiof"; |
| reg = <0 0xe6c10000 0 0x0064>; |
| interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 208>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 208>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| vin4: video@e6ef4000 { |
| compatible = "renesas,vin-r8a77990"; |
| reg = <0 0xe6ef4000 0 0x1000>; |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 807>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 807>; |
| renesas,id = <4>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@1 { |
| reg = <1>; |
| |
| vin4csi40: endpoint { |
| remote-endpoint= <&csi40vin4>; |
| }; |
| }; |
| }; |
| }; |
| |
| vin5: video@e6ef5000 { |
| compatible = "renesas,vin-r8a77990"; |
| reg = <0 0xe6ef5000 0 0x1000>; |
| interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 806>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 806>; |
| renesas,id = <5>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@1 { |
| reg = <1>; |
| |
| vin5csi40: endpoint { |
| remote-endpoint= <&csi40vin5>; |
| }; |
| }; |
| }; |
| }; |
| |
| xhci0: usb@ee000000 { |
| compatible = "renesas,xhci-r8a77990", |
| "renesas,rcar-gen3-xhci"; |
| reg = <0 0xee000000 0 0xc00>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 328>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 328>; |
| status = "disabled"; |
| }; |
| |
| ohci0: usb@ee080000 { |
| compatible = "generic-ohci"; |
| reg = <0 0xee080000 0 0x100>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| phys = <&usb2_phy0>; |
| phy-names = "usb"; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 703>, <&cpg 704>; |
| status = "disabled"; |
| }; |
| |
| ehci0: usb@ee080100 { |
| compatible = "generic-ehci"; |
| reg = <0 0xee080100 0 0x100>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| phys = <&usb2_phy0>; |
| phy-names = "usb"; |
| companion = <&ohci0>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 703>, <&cpg 704>; |
| status = "disabled"; |
| }; |
| |
| usb2_phy0: usb-phy@ee080200 { |
| compatible = "renesas,usb2-phy-r8a77990", |
| "renesas,rcar-gen3-usb2-phy"; |
| reg = <0 0xee080200 0 0x700>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 703>, <&cpg 704>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@f1010000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xf1010000 0 0x1000>, |
| <0x0 0xf1020000 0 0x20000>, |
| <0x0 0xf1040000 0 0x20000>, |
| <0x0 0xf1060000 0 0x20000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| clocks = <&cpg CPG_MOD 408>; |
| clock-names = "clk"; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 408>; |
| }; |
| |
| vspb0: vsp@fe960000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfe960000 0 0x8000>; |
| interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 626>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 626>; |
| renesas,fcp = <&fcpvb0>; |
| }; |
| |
| fcpvb0: fcp@fe96f000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfe96f000 0 0x200>; |
| clocks = <&cpg CPG_MOD 607>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 607>; |
| iommus = <&ipmmu_vp0 5>; |
| }; |
| |
| vspi0: vsp@fe9a0000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfe9a0000 0 0x8000>; |
| interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 631>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 631>; |
| renesas,fcp = <&fcpvi0>; |
| }; |
| |
| fcpvi0: fcp@fe9af000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfe9af000 0 0x200>; |
| clocks = <&cpg CPG_MOD 611>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 611>; |
| iommus = <&ipmmu_vp0 8>; |
| }; |
| |
| vspd0: vsp@fea20000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfea20000 0 0x7000>; |
| interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 623>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 623>; |
| renesas,fcp = <&fcpvd0>; |
| }; |
| |
| fcpvd0: fcp@fea27000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfea27000 0 0x200>; |
| clocks = <&cpg CPG_MOD 603>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 603>; |
| iommus = <&ipmmu_vi0 8>; |
| }; |
| |
| vspd1: vsp@fea28000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfea28000 0 0x7000>; |
| interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 622>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 622>; |
| renesas,fcp = <&fcpvd1>; |
| }; |
| |
| fcpvd1: fcp@fea2f000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfea2f000 0 0x200>; |
| clocks = <&cpg CPG_MOD 602>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 602>; |
| iommus = <&ipmmu_vi0 9>; |
| }; |
| |
| csi40: csi2@feaa0000 { |
| compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; |
| reg = <0 0xfeaa0000 0 0x10000>; |
| interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 716>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 716>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg = <1>; |
| |
| csi40vin4: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&vin4csi40>; |
| }; |
| csi40vin5: endpoint@1 { |
| reg = <1>; |
| remote-endpoint = <&vin5csi40>; |
| }; |
| }; |
| }; |
| }; |
| |
| du: display@feb00000 { |
| compatible = "renesas,du-r8a77990"; |
| reg = <0 0xfeb00000 0 0x80000>; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 724>, |
| <&cpg CPG_MOD 723>; |
| clock-names = "du.0", "du.1"; |
| vsps = <&vspd0 0 &vspd1 0>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| du_out_rgb: endpoint { |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| du_out_lvds0: endpoint { |
| remote-endpoint = <&lvds0_in>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| du_out_lvds1: endpoint { |
| remote-endpoint = <&lvds1_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| lvds0: lvds-encoder@feb90000 { |
| compatible = "renesas,r8a77990-lvds"; |
| reg = <0 0xfeb90000 0 0x20>; |
| clocks = <&cpg CPG_MOD 727>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 727>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| lvds0_in: endpoint { |
| remote-endpoint = <&du_out_lvds0>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| lvds0_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| lvds1: lvds-encoder@feb90100 { |
| compatible = "renesas,r8a77990-lvds"; |
| reg = <0 0xfeb90100 0 0x20>; |
| clocks = <&cpg CPG_MOD 727>; |
| power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; |
| resets = <&cpg 726>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| lvds1_in: endpoint { |
| remote-endpoint = <&du_out_lvds1>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| lvds1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| prr: chipid@fff00044 { |
| compatible = "renesas,prr"; |
| reg = <0 0xfff00044 0 4>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |