| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| title: Xilinx clocking wizard |
| - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> |
| The clocking wizard is a soft ip clocking block of Xilinx versal. It |
| reads required input clock frequencies from the devicetree and acts as clock |
| - xlnx,clocking-wizard-v5.2 |
| - xlnx,clocking-wizard-v6.0 |
| - description: clock input |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| Speed grade of the device. Higher the speed grade faster is the FPGA device. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| additionalProperties: false |
| clock-controller@b0000000 { |
| compatible = "xlnx,clocking-wizard"; |
| reg = <0xb0000000 0x10000>; |
| clock-names = "clk_in1", "s_axi_aclk"; |
| clocks = <&clkc 15>, <&clkc 15>; |