| [ |
| { |
| "MetricExpr": "INST_RETIRED.ANY / cycles", |
| "BriefDescription": "Instructions Per Cycle (per Logical Processor)", |
| "MetricName": "IPC" |
| }, |
| { |
| "MetricExpr": "1 / IPC", |
| "BriefDescription": "Cycles Per Instruction (per Logical Processor)", |
| "MetricName": "CPI" |
| }, |
| { |
| "MetricExpr": "cycles", |
| "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", |
| "MetricName": "CLKS" |
| }, |
| { |
| "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", |
| "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", |
| "MetricName": "IpMispredict" |
| }, |
| { |
| "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", |
| "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", |
| "MetricName": "IpBranch" |
| }, |
| { |
| "MetricExpr": "INST_RETIRED.ANY", |
| "BriefDescription": "Total number of retired Instructions", |
| "MetricName": "Instructions" |
| }, |
| { |
| "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 ", |
| "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", |
| "MetricName": "L3_Cache_Fill_BW" |
| }, |
| { |
| "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", |
| "BriefDescription": "Average CPU Utilization", |
| "MetricName": "CPU_Utilization" |
| }, |
| { |
| "MetricExpr": "(cycles / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 ", |
| "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", |
| "MetricName": "Average_Frequency" |
| }, |
| { |
| "MetricExpr": "cycles / CPU_CLK_UNHALTED.REF_TSC", |
| "BriefDescription": "Average Frequency Utilization relative nominal frequency", |
| "MetricName": "Turbo_Utilization" |
| }, |
| { |
| "MetricExpr": "cycles:k / cycles", |
| "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", |
| "MetricName": "Kernel_Utilization" |
| } |
| ] |
