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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek switches for unmanaged switches
allOf:
- $ref: dsa.yaml#
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description:
Realtek advertises these chips as fast/gigabit switches or unmanaged
switches. They can be controlled using different interfaces, like SMI,
MDIO or SPI.
The SMI "Simple Management Interface" is a two-wire protocol using
bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
not use the MDIO protocol. This binding defines how to specify the
SMI-based Realtek devices. The realtek-smi driver is a platform driver
and it must be inserted inside a platform node.
The MDIO-connected switches use MDIO protocol to access their registers.
The realtek-mdio driver is an MDIO driver and it must be inserted inside
an MDIO node.
properties:
compatible:
enum:
- realtek,rtl8365mb
- realtek,rtl8366
- realtek,rtl8366rb
- realtek,rtl8366s
- realtek,rtl8367
- realtek,rtl8367b
- realtek,rtl8367rb
- realtek,rtl8367s
- realtek,rtl8368s
- realtek,rtl8369
- realtek,rtl8370
description: |
realtek,rtl8365mb: 4+1 ports
realtek,rtl8366: 5+1 ports
realtek,rtl8366rb: 5+1 ports
realtek,rtl8366s: 5+1 ports
realtek,rtl8367:
realtek,rtl8367b:
realtek,rtl8367rb: 5+2 ports
realtek,rtl8367s: 5+2 ports
realtek,rtl8368s: 8 ports
realtek,rtl8369: 8+1 ports
realtek,rtl8370: 8+2 ports
mdc-gpios:
description: GPIO line for the MDC clock line.
maxItems: 1
mdio-gpios:
description: GPIO line for the MDIO data line.
maxItems: 1
reset-gpios:
description: GPIO to be used to reset the whole device
maxItems: 1
realtek,disable-leds:
type: boolean
description: |
if the LED drivers are not used in the hardware design,
this will disable them so they are not turned on
and wasting power.
interrupt-controller:
type: object
description: |
This defines an interrupt controller with an IRQ line (typically
a GPIO) that will demultiplex and handle the interrupt from the single
interrupt line coming out of one of the Realtek switch chips. It most
importantly provides link up/down interrupts to the PHY blocks inside
the ASIC.
properties:
interrupt-controller: true
interrupts:
maxItems: 1
description:
A single IRQ line from the switch, either active LOW or HIGH
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
required:
- interrupt-controller
- '#address-cells'
- '#interrupt-cells'
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
properties:
compatible:
const: realtek,smi-mdio
if:
required:
- reg
then:
not:
required:
- mdc-gpios
- mdio-gpios
- mdio
properties:
mdc-gpios: false
mdio-gpios: false
mdio: false
else:
required:
- mdc-gpios
- mdio-gpios
- mdio
- reset-gpios
required:
- compatible
# - mdc-gpios
# - mdio-gpios
# - reset-gpios
# - mdio
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
platform {
switch {
compatible = "realtek,rtl8366rb";
/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
switch_intc1: interrupt-controller {
/* GPIO 15 provides the interrupt */
interrupt-parent = <&gpio0>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&phy3>;
};
port@4 {
reg = <4>;
label = "wan";
phy-handle = <&phy4>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
compatible = "realtek,smi-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch_intc1>;
interrupts = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch_intc1>;
interrupts = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch_intc1>;
interrupts = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch_intc1>;
interrupts = <3>;
};
phy4: ethernet-phy@4 {
reg = <4>;
interrupt-parent = <&switch_intc1>;
interrupts = <12>;
};
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
platform {
switch {
compatible = "realtek,rtl8365mb";
mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
switch_intc2: interrupt-controller {
interrupt-parent = <&gpio5>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "swp0";
phy-handle = <&ethphy0>;
};
port@1 {
reg = <1>;
label = "swp1";
phy-handle = <&ethphy1>;
};
port@2 {
reg = <2>;
label = "swp2";
phy-handle = <&ethphy2>;
};
port@3 {
reg = <3>;
label = "swp3";
phy-handle = <&ethphy3>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&fec1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <2000>;
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
mdio {
compatible = "realtek,smi-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch_intc2>;
interrupts = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch_intc2>;
interrupts = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch_intc2>;
interrupts = <2>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch_intc2>;
interrupts = <3>;
};
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch@29 {
compatible = "realtek,rtl8367s";
reg = <29>;
reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
switch_intc3: interrupt-controller {
interrupt-parent = <&gpio0>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@7 {
reg = <7>;
ethernet = <&ethernet>;
phy-mode = "rgmii";
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};