| // SPDX-License-Identifier: GPL-2.0-only |
| // |
| // rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver |
| // |
| // Copyright(c) 2024 Realtek Semiconductor Corp. |
| // |
| // |
| #include <linux/delay.h> |
| #include <linux/device.h> |
| #include <linux/pm_runtime.h> |
| #include <linux/mod_devicetable.h> |
| #include <linux/module.h> |
| #include <linux/regmap.h> |
| #include <linux/dmi.h> |
| #include <linux/firmware.h> |
| #include <sound/core.h> |
| #include <sound/pcm.h> |
| #include <sound/pcm_params.h> |
| #include <sound/soc-dapm.h> |
| #include <sound/initval.h> |
| #include <sound/tlv.h> |
| #include <sound/sdw.h> |
| #include "rt1320-sdw.h" |
| |
| /* |
| * The 'blind writes' is an SDCA term to deal with platform-specific initialization. |
| * It might include vendor-specific or SDCA control registers. |
| */ |
| static const struct reg_sequence rt1320_blind_write[] = { |
| { 0xc003, 0xe0 }, |
| { 0xc01b, 0xfc }, |
| { 0xc5c3, 0xf2 }, |
| { 0xc5c2, 0x00 }, |
| { 0xc5c6, 0x10 }, |
| { 0xc5c4, 0x12 }, |
| { 0xc5c8, 0x03 }, |
| { 0xc5d8, 0x0a }, |
| { 0xc5f7, 0x22 }, |
| { 0xc5f6, 0x22 }, |
| { 0xc5d0, 0x0f }, |
| { 0xc5d1, 0x89 }, |
| { 0xc057, 0x51 }, |
| { 0xc054, 0x35 }, |
| { 0xc053, 0x55 }, |
| { 0xc052, 0x55 }, |
| { 0xc051, 0x13 }, |
| { 0xc050, 0x15 }, |
| { 0xc060, 0x77 }, |
| { 0xc061, 0x55 }, |
| { 0xc063, 0x55 }, |
| { 0xc065, 0xa5 }, |
| { 0xc06b, 0x0a }, |
| { 0xca05, 0xd6 }, |
| { 0xca25, 0xd6 }, |
| { 0xcd00, 0x05 }, |
| { 0xc604, 0x40 }, |
| { 0xc609, 0x40 }, |
| { 0xc046, 0xff }, |
| { 0xc045, 0xff }, |
| { 0xc044, 0xff }, |
| { 0xc043, 0xff }, |
| { 0xc042, 0xff }, |
| { 0xc041, 0xff }, |
| { 0xc040, 0xff }, |
| { 0xcc10, 0x01 }, |
| { 0xc700, 0xf0 }, |
| { 0xc701, 0x13 }, |
| { 0xc901, 0x04 }, |
| { 0xc900, 0x73 }, |
| { 0xde03, 0x05 }, |
| { 0xdd0b, 0x0d }, |
| { 0xdd0a, 0xff }, |
| { 0xdd09, 0x0d }, |
| { 0xdd08, 0xff }, |
| { 0xc570, 0x08 }, |
| { 0xe803, 0xbe }, |
| { 0xc003, 0xc0 }, |
| { 0xc081, 0xfe }, |
| { 0xce31, 0x0d }, |
| { 0xce30, 0xae }, |
| { 0xce37, 0x0b }, |
| { 0xce36, 0xd2 }, |
| { 0xce39, 0x04 }, |
| { 0xce38, 0x80 }, |
| { 0xce3f, 0x00 }, |
| { 0xce3e, 0x00 }, |
| { 0xd470, 0x8b }, |
| { 0xd471, 0x18 }, |
| { 0xc019, 0x10 }, |
| { 0xd487, 0x3f }, |
| { 0xd486, 0xc3 }, |
| }; |
| |
| static const struct reg_sequence rt1320_vc_blind_write[] = { |
| { 0xc003, 0xe0 }, |
| { 0xe80a, 0x01 }, |
| { 0xc5c3, 0xf3 }, |
| { 0xc057, 0x51 }, |
| { 0xc054, 0x35 }, |
| { 0xca05, 0xd6 }, |
| { 0xca07, 0x07 }, |
| { 0xca25, 0xd6 }, |
| { 0xca27, 0x07 }, |
| { 0xc604, 0x40 }, |
| { 0xc609, 0x40 }, |
| { 0xc046, 0xff }, |
| { 0xc045, 0xff }, |
| { 0xda81, 0x14 }, |
| { 0xda8d, 0x14 }, |
| { 0xc044, 0xff }, |
| { 0xc043, 0xff }, |
| { 0xc042, 0xff }, |
| { 0xc041, 0x7f }, |
| { 0xc040, 0xff }, |
| { 0xcc10, 0x01 }, |
| { 0xc700, 0xf0 }, |
| { 0xc701, 0x13 }, |
| { 0xc901, 0x09 }, |
| { 0xc900, 0xd0 }, |
| { 0xde03, 0x05 }, |
| { 0xdd0b, 0x0d }, |
| { 0xdd0a, 0xff }, |
| { 0xdd09, 0x0d }, |
| { 0xdd08, 0xff }, |
| { 0xc570, 0x08 }, |
| { 0xc086, 0x02 }, |
| { 0xc085, 0x7f }, |
| { 0xc084, 0x00 }, |
| { 0xc081, 0xfe }, |
| { 0xf084, 0x0f }, |
| { 0xf083, 0xff }, |
| { 0xf082, 0xff }, |
| { 0xf081, 0xff }, |
| { 0xf080, 0xff }, |
| { 0xe802, 0xf8 }, |
| { 0xe803, 0xbe }, |
| { 0xc003, 0xc0 }, |
| { 0xd470, 0xec }, |
| { 0xd471, 0x3a }, |
| { 0xd474, 0x11 }, |
| { 0xd475, 0x32 }, |
| { 0xd478, 0x64 }, |
| { 0xd479, 0x20 }, |
| { 0xd47a, 0x10 }, |
| { 0xd47c, 0xff }, |
| { 0xc019, 0x10 }, |
| { 0xd487, 0x0b }, |
| { 0xd487, 0x3b }, |
| { 0xd486, 0xc3 }, |
| { 0xc598, 0x04 }, |
| { 0xd500, 0x00 }, |
| { 0xd500, 0x17 }, |
| { 0xd600, 0x01 }, |
| { 0xd601, 0x02 }, |
| { 0xd602, 0x03 }, |
| { 0xd603, 0x04 }, |
| { 0xd64c, 0x03 }, |
| { 0xd64d, 0x03 }, |
| { 0xd64e, 0x03 }, |
| { 0xd64f, 0x03 }, |
| { 0xd650, 0x03 }, |
| { 0xd651, 0x03 }, |
| { 0xd652, 0x03 }, |
| { 0xd610, 0x01 }, |
| { 0xd608, 0x03 }, |
| { 0xd609, 0x00 }, |
| }; |
| |
| static const struct reg_sequence rt1320_vc_patch_code_write[] = { |
| { 0x10007000, 0x37 }, |
| { 0x10007001, 0x77 }, |
| { 0x10007002, 0x00 }, |
| { 0x10007003, 0x10 }, |
| { 0x10007004, 0xb7 }, |
| { 0x10007005, 0xe7 }, |
| { 0x10007006, 0x00 }, |
| { 0x10007007, 0x10 }, |
| { 0x10007008, 0x13 }, |
| { 0x10007009, 0x07 }, |
| { 0x1000700a, 0x87 }, |
| { 0x1000700b, 0x48 }, |
| { 0x1000700c, 0x23 }, |
| { 0x1000700d, 0xa6 }, |
| { 0x1000700e, 0xe7 }, |
| { 0x1000700f, 0xee }, |
| { 0x10007010, 0x37 }, |
| { 0x10007011, 0x77 }, |
| { 0x10007012, 0x00 }, |
| { 0x10007013, 0x10 }, |
| { 0x10007014, 0x13 }, |
| { 0x10007015, 0x07 }, |
| { 0x10007016, 0x87 }, |
| { 0x10007017, 0x56 }, |
| { 0x10007018, 0x23 }, |
| { 0x10007019, 0xac }, |
| { 0x1000701a, 0xe7 }, |
| { 0x1000701b, 0xde }, |
| { 0x1000701c, 0x37 }, |
| { 0x1000701d, 0x77 }, |
| { 0x1000701e, 0x00 }, |
| { 0x1000701f, 0x10 }, |
| { 0x10007020, 0x13 }, |
| { 0x10007021, 0x07 }, |
| { 0x10007022, 0xc7 }, |
| { 0x10007023, 0x5f }, |
| { 0x10007024, 0x23 }, |
| { 0x10007025, 0xae }, |
| { 0x10007026, 0xe7 }, |
| { 0x10007027, 0xdc }, |
| { 0x10007028, 0x37 }, |
| { 0x10007029, 0x87 }, |
| { 0x1000702a, 0x00 }, |
| { 0x1000702b, 0x10 }, |
| { 0x1000702c, 0x13 }, |
| { 0x1000702d, 0x07 }, |
| { 0x1000702e, 0xc7 }, |
| { 0x1000702f, 0x86 }, |
| { 0x10007030, 0x23 }, |
| { 0x10007031, 0xae }, |
| { 0x10007032, 0xe7 }, |
| { 0x10007033, 0xe6 }, |
| { 0x10007034, 0x37 }, |
| { 0x10007035, 0x77 }, |
| { 0x10007036, 0x00 }, |
| { 0x10007037, 0x10 }, |
| { 0x10007038, 0x13 }, |
| { 0x10007039, 0x07 }, |
| { 0x1000703a, 0x07 }, |
| { 0x1000703b, 0x40 }, |
| { 0x1000703c, 0x23 }, |
| { 0x1000703d, 0xa6 }, |
| { 0x1000703e, 0xe7 }, |
| { 0x1000703f, 0xe8 }, |
| { 0x10007040, 0x37 }, |
| { 0x10007041, 0x77 }, |
| { 0x10007042, 0x00 }, |
| { 0x10007043, 0x10 }, |
| { 0x10007044, 0x13 }, |
| { 0x10007045, 0x07 }, |
| { 0x10007046, 0xc7 }, |
| { 0x10007047, 0x63 }, |
| { 0x10007048, 0x23 }, |
| { 0x10007049, 0xa2 }, |
| { 0x1000704a, 0xe7 }, |
| { 0x1000704b, 0xec }, |
| { 0x1000704c, 0x37 }, |
| { 0x1000704d, 0x77 }, |
| { 0x1000704e, 0x00 }, |
| { 0x1000704f, 0x10 }, |
| { 0x10007050, 0x13 }, |
| { 0x10007051, 0x07 }, |
| { 0x10007052, 0x47 }, |
| { 0x10007053, 0x6f }, |
| { 0x10007054, 0x23 }, |
| { 0x10007055, 0xa6 }, |
| { 0x10007056, 0xe7 }, |
| { 0x10007057, 0xec }, |
| { 0x10007058, 0x37 }, |
| { 0x10007059, 0x77 }, |
| { 0x1000705a, 0x00 }, |
| { 0x1000705b, 0x10 }, |
| { 0x1000705c, 0x13 }, |
| { 0x1000705d, 0x07 }, |
| { 0x1000705e, 0x07 }, |
| { 0x1000705f, 0x44 }, |
| { 0x10007060, 0x23 }, |
| { 0x10007061, 0xa8 }, |
| { 0x10007062, 0xe7 }, |
| { 0x10007063, 0xec }, |
| { 0x10007064, 0x37 }, |
| { 0x10007065, 0x87 }, |
| { 0x10007066, 0x00 }, |
| { 0x10007067, 0x10 }, |
| { 0x10007068, 0x13 }, |
| { 0x10007069, 0x07 }, |
| { 0x1000706a, 0x87 }, |
| { 0x1000706b, 0x84 }, |
| { 0x1000706c, 0x23 }, |
| { 0x1000706d, 0xa8 }, |
| { 0x1000706e, 0xe7 }, |
| { 0x1000706f, 0xee }, |
| { 0x10007070, 0x37 }, |
| { 0x10007071, 0x87 }, |
| { 0x10007072, 0x00 }, |
| { 0x10007073, 0x10 }, |
| { 0x10007074, 0x13 }, |
| { 0x10007075, 0x07 }, |
| { 0x10007076, 0x47 }, |
| { 0x10007077, 0x97 }, |
| { 0x10007078, 0x23 }, |
| { 0x10007079, 0xaa }, |
| { 0x1000707a, 0xe7 }, |
| { 0x1000707b, 0xee }, |
| { 0x1000707c, 0x67 }, |
| { 0x1000707d, 0x80 }, |
| { 0x1000707e, 0x00 }, |
| { 0x1000707f, 0x00 }, |
| { 0x10007400, 0xb7 }, |
| { 0x10007401, 0xd6 }, |
| { 0x10007402, 0x00 }, |
| { 0x10007403, 0x00 }, |
| { 0x10007404, 0x83 }, |
| { 0x10007405, 0xc7 }, |
| { 0x10007406, 0x06 }, |
| { 0x10007407, 0x47 }, |
| { 0x10007408, 0x93 }, |
| { 0x10007409, 0xf7 }, |
| { 0x1000740a, 0x87 }, |
| { 0x1000740b, 0x00 }, |
| { 0x1000740c, 0x63 }, |
| { 0x1000740d, 0x88 }, |
| { 0x1000740e, 0x07 }, |
| { 0x1000740f, 0x02 }, |
| { 0x10007410, 0x03 }, |
| { 0x10007411, 0xc7 }, |
| { 0x10007412, 0x31 }, |
| { 0x10007413, 0x43 }, |
| { 0x10007414, 0x63 }, |
| { 0x10007415, 0x14 }, |
| { 0x10007416, 0x07 }, |
| { 0x10007417, 0x02 }, |
| { 0x10007418, 0x13 }, |
| { 0x10007419, 0x07 }, |
| { 0x1000741a, 0x10 }, |
| { 0x1000741b, 0x00 }, |
| { 0x1000741c, 0xa3 }, |
| { 0x1000741d, 0x89 }, |
| { 0x1000741e, 0xe1 }, |
| { 0x1000741f, 0x42 }, |
| { 0x10007420, 0x37 }, |
| { 0x10007421, 0xc7 }, |
| { 0x10007422, 0x00 }, |
| { 0x10007423, 0x00 }, |
| { 0x10007424, 0x03 }, |
| { 0x10007425, 0x46 }, |
| { 0x10007426, 0x07 }, |
| { 0x10007427, 0x06 }, |
| { 0x10007428, 0x23 }, |
| { 0x10007429, 0x8a }, |
| { 0x1000742a, 0xc1 }, |
| { 0x1000742b, 0x42 }, |
| { 0x1000742c, 0x83 }, |
| { 0x1000742d, 0xc7 }, |
| { 0x1000742e, 0x46 }, |
| { 0x1000742f, 0x47 }, |
| { 0x10007430, 0x93 }, |
| { 0x10007431, 0xf7 }, |
| { 0x10007432, 0xf7 }, |
| { 0x10007433, 0x0f }, |
| { 0x10007434, 0x23 }, |
| { 0x10007435, 0x00 }, |
| { 0x10007436, 0xf7 }, |
| { 0x10007437, 0x06 }, |
| { 0x10007438, 0x23 }, |
| { 0x10007439, 0x89 }, |
| { 0x1000743a, 0x01 }, |
| { 0x1000743b, 0x42 }, |
| { 0x1000743c, 0x67 }, |
| { 0x1000743d, 0x80 }, |
| { 0x1000743e, 0x00 }, |
| { 0x1000743f, 0x00 }, |
| { 0x10007440, 0x37 }, |
| { 0x10007441, 0xc7 }, |
| { 0x10007442, 0x00 }, |
| { 0x10007443, 0x00 }, |
| { 0x10007444, 0x83 }, |
| { 0x10007445, 0x27 }, |
| { 0x10007446, 0xc7 }, |
| { 0x10007447, 0x5f }, |
| { 0x10007448, 0x13 }, |
| { 0x10007449, 0x05 }, |
| { 0x1000744a, 0x00 }, |
| { 0x1000744b, 0x00 }, |
| { 0x1000744c, 0x23 }, |
| { 0x1000744d, 0xa2 }, |
| { 0x1000744e, 0xf1 }, |
| { 0x1000744f, 0x42 }, |
| { 0x10007450, 0xb7 }, |
| { 0x10007451, 0x06 }, |
| { 0x10007452, 0x00 }, |
| { 0x10007453, 0x10 }, |
| { 0x10007454, 0xb3 }, |
| { 0x10007455, 0xf7 }, |
| { 0x10007456, 0xd7 }, |
| { 0x10007457, 0x00 }, |
| { 0x10007458, 0x63 }, |
| { 0x10007459, 0x86 }, |
| { 0x1000745a, 0x07 }, |
| { 0x1000745b, 0x02 }, |
| { 0x1000745c, 0x83 }, |
| { 0x1000745d, 0x47 }, |
| { 0x1000745e, 0x07 }, |
| { 0x1000745f, 0x56 }, |
| { 0x10007460, 0x93 }, |
| { 0x10007461, 0xf7 }, |
| { 0x10007462, 0x87 }, |
| { 0x10007463, 0x01 }, |
| { 0x10007464, 0x63 }, |
| { 0x10007465, 0x80 }, |
| { 0x10007466, 0x07 }, |
| { 0x10007467, 0x02 }, |
| { 0x10007468, 0x83 }, |
| { 0x10007469, 0x47 }, |
| { 0x1000746a, 0x17 }, |
| { 0x1000746b, 0x08 }, |
| { 0x1000746c, 0x93 }, |
| { 0x1000746d, 0xf7 }, |
| { 0x1000746e, 0x47 }, |
| { 0x1000746f, 0x00 }, |
| { 0x10007470, 0x63 }, |
| { 0x10007471, 0x8a }, |
| { 0x10007472, 0x07 }, |
| { 0x10007473, 0x00 }, |
| { 0x10007474, 0xb7 }, |
| { 0x10007475, 0xc7 }, |
| { 0x10007476, 0xc2 }, |
| { 0x10007477, 0x3f }, |
| { 0x10007478, 0x03 }, |
| { 0x10007479, 0xa5 }, |
| { 0x1000747a, 0x47 }, |
| { 0x1000747b, 0xfc }, |
| { 0x1000747c, 0x13 }, |
| { 0x1000747d, 0x55 }, |
| { 0x1000747e, 0x25 }, |
| { 0x1000747f, 0x00 }, |
| { 0x10007480, 0x13 }, |
| { 0x10007481, 0x75 }, |
| { 0x10007482, 0x15 }, |
| { 0x10007483, 0x00 }, |
| { 0x10007484, 0x67 }, |
| { 0x10007485, 0x80 }, |
| { 0x10007486, 0x00 }, |
| { 0x10007487, 0x00 }, |
| { 0x10007488, 0x03 }, |
| { 0x10007489, 0xa7 }, |
| { 0x1000748a, 0x81 }, |
| { 0x1000748b, 0x57 }, |
| { 0x1000748c, 0x13 }, |
| { 0x1000748d, 0x01 }, |
| { 0x1000748e, 0x01 }, |
| { 0x1000748f, 0xff }, |
| { 0x10007490, 0x23 }, |
| { 0x10007491, 0x26 }, |
| { 0x10007492, 0x11 }, |
| { 0x10007493, 0x00 }, |
| { 0x10007494, 0x23 }, |
| { 0x10007495, 0x24 }, |
| { 0x10007496, 0x81 }, |
| { 0x10007497, 0x00 }, |
| { 0x10007498, 0x23 }, |
| { 0x10007499, 0x22 }, |
| { 0x1000749a, 0x91 }, |
| { 0x1000749b, 0x00 }, |
| { 0x1000749c, 0x93 }, |
| { 0x1000749d, 0x07 }, |
| { 0x1000749e, 0xa0 }, |
| { 0x1000749f, 0x05 }, |
| { 0x100074a0, 0x63 }, |
| { 0x100074a1, 0x14 }, |
| { 0x100074a2, 0xf7 }, |
| { 0x100074a3, 0x04 }, |
| { 0x100074a4, 0x37 }, |
| { 0x100074a5, 0x07 }, |
| { 0x100074a6, 0x00 }, |
| { 0x100074a7, 0x11 }, |
| { 0x100074a8, 0x83 }, |
| { 0x100074a9, 0x47 }, |
| { 0x100074aa, 0x07 }, |
| { 0x100074ab, 0x01 }, |
| { 0x100074ac, 0x13 }, |
| { 0x100074ad, 0x06 }, |
| { 0x100074ae, 0x30 }, |
| { 0x100074af, 0x00 }, |
| { 0x100074b0, 0x93 }, |
| { 0x100074b1, 0xf7 }, |
| { 0x100074b2, 0xf7 }, |
| { 0x100074b3, 0x0f }, |
| { 0x100074b4, 0x63 }, |
| { 0x100074b5, 0x9a }, |
| { 0x100074b6, 0xc7 }, |
| { 0x100074b7, 0x02 }, |
| { 0x100074b8, 0x03 }, |
| { 0x100074b9, 0x47 }, |
| { 0x100074ba, 0x87 }, |
| { 0x100074bb, 0x01 }, |
| { 0x100074bc, 0x13 }, |
| { 0x100074bd, 0x77 }, |
| { 0x100074be, 0xf7 }, |
| { 0x100074bf, 0x0f }, |
| { 0x100074c0, 0x63 }, |
| { 0x100074c1, 0x14 }, |
| { 0x100074c2, 0xf7 }, |
| { 0x100074c3, 0x02 }, |
| { 0x100074c4, 0x37 }, |
| { 0x100074c5, 0xd7 }, |
| { 0x100074c6, 0x00 }, |
| { 0x100074c7, 0x00 }, |
| { 0x100074c8, 0x83 }, |
| { 0x100074c9, 0x47 }, |
| { 0x100074ca, 0x37 }, |
| { 0x100074cb, 0x54 }, |
| { 0x100074cc, 0x93 }, |
| { 0x100074cd, 0xf7 }, |
| { 0x100074ce, 0xf7 }, |
| { 0x100074cf, 0x0f }, |
| { 0x100074d0, 0x93 }, |
| { 0x100074d1, 0xe7 }, |
| { 0x100074d2, 0x07 }, |
| { 0x100074d3, 0x02 }, |
| { 0x100074d4, 0xa3 }, |
| { 0x100074d5, 0x01 }, |
| { 0x100074d6, 0xf7 }, |
| { 0x100074d7, 0x54 }, |
| { 0x100074d8, 0x83 }, |
| { 0x100074d9, 0x47 }, |
| { 0x100074da, 0x37 }, |
| { 0x100074db, 0x54 }, |
| { 0x100074dc, 0x93 }, |
| { 0x100074dd, 0xf7 }, |
| { 0x100074de, 0xf7 }, |
| { 0x100074df, 0x0d }, |
| { 0x100074e0, 0xa3 }, |
| { 0x100074e1, 0x01 }, |
| { 0x100074e2, 0xf7 }, |
| { 0x100074e3, 0x54 }, |
| { 0x100074e4, 0x23 }, |
| { 0x100074e5, 0xac }, |
| { 0x100074e6, 0x01 }, |
| { 0x100074e7, 0x56 }, |
| { 0x100074e8, 0x37 }, |
| { 0x100074e9, 0xd4 }, |
| { 0x100074ea, 0x00 }, |
| { 0x100074eb, 0x00 }, |
| { 0x100074ec, 0x83 }, |
| { 0x100074ed, 0x47 }, |
| { 0x100074ee, 0xd4 }, |
| { 0x100074ef, 0x47 }, |
| { 0x100074f0, 0x93 }, |
| { 0x100074f1, 0xf7 }, |
| { 0x100074f2, 0x17 }, |
| { 0x100074f3, 0x00 }, |
| { 0x100074f4, 0x63 }, |
| { 0x100074f5, 0x80 }, |
| { 0x100074f6, 0x07 }, |
| { 0x100074f7, 0x06 }, |
| { 0x100074f8, 0x37 }, |
| { 0x100074f9, 0xd7 }, |
| { 0x100074fa, 0x00 }, |
| { 0x100074fb, 0x10 }, |
| { 0x100074fc, 0x83 }, |
| { 0x100074fd, 0x47 }, |
| { 0x100074fe, 0x77 }, |
| { 0x100074ff, 0xd9 }, |
| { 0x10007500, 0x93 }, |
| { 0x10007501, 0x87 }, |
| { 0x10007502, 0x17 }, |
| { 0x10007503, 0x00 }, |
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| { 0x1000792b, 0x0f }, |
| { 0x1000792c, 0xe3 }, |
| { 0x1000792d, 0x02 }, |
| { 0x1000792e, 0xf7 }, |
| { 0x1000792f, 0xfa }, |
| { 0x10007930, 0xb7 }, |
| { 0x10007931, 0xc7 }, |
| { 0x10007932, 0x00 }, |
| { 0x10007933, 0x00 }, |
| { 0x10007934, 0x83 }, |
| { 0x10007935, 0xc7 }, |
| { 0x10007936, 0x07 }, |
| { 0x10007937, 0x56 }, |
| { 0x10007938, 0x13 }, |
| { 0x10007939, 0x07 }, |
| { 0x1000793a, 0xf0 }, |
| { 0x1000793b, 0x00 }, |
| { 0x1000793c, 0x93 }, |
| { 0x1000793d, 0xf7 }, |
| { 0x1000793e, 0xf7 }, |
| { 0x1000793f, 0x0f }, |
| { 0x10007940, 0xe3 }, |
| { 0x10007941, 0x78 }, |
| { 0x10007942, 0xf7 }, |
| { 0x10007943, 0xf8 }, |
| { 0x10007944, 0xb7 }, |
| { 0x10007945, 0xd7 }, |
| { 0x10007946, 0x00 }, |
| { 0x10007947, 0x00 }, |
| { 0x10007948, 0x83 }, |
| { 0x10007949, 0xc5 }, |
| { 0x1000794a, 0xa7 }, |
| { 0x1000794b, 0x47 }, |
| { 0x1000794c, 0x93 }, |
| { 0x1000794d, 0xf7 }, |
| { 0x1000794e, 0xf5 }, |
| { 0x1000794f, 0x0f }, |
| { 0x10007950, 0x93 }, |
| { 0x10007951, 0x95 }, |
| { 0x10007952, 0x57 }, |
| { 0x10007953, 0x00 }, |
| { 0x10007954, 0xb3 }, |
| { 0x10007955, 0x85 }, |
| { 0x10007956, 0xf5 }, |
| { 0x10007957, 0x40 }, |
| { 0x10007958, 0x93 }, |
| { 0x10007959, 0x95 }, |
| { 0x1000795a, 0x25 }, |
| { 0x1000795b, 0x00 }, |
| { 0x1000795c, 0xb3 }, |
| { 0x1000795d, 0x85 }, |
| { 0x1000795e, 0xf5 }, |
| { 0x1000795f, 0x00 }, |
| { 0x10007960, 0x13 }, |
| { 0x10007961, 0x95 }, |
| { 0x10007962, 0x35 }, |
| { 0x10007963, 0x00 }, |
| { 0x10007964, 0x93 }, |
| { 0x10007965, 0xd5 }, |
| { 0x10007966, 0xf5 }, |
| { 0x10007967, 0x41 }, |
| { 0x10007968, 0xef }, |
| { 0x10007969, 0xe0 }, |
| { 0x1000796a, 0xcf }, |
| { 0x1000796b, 0x8b }, |
| { 0x1000796c, 0x03 }, |
| { 0x1000796d, 0xc7 }, |
| { 0x1000796e, 0xd1 }, |
| { 0x1000796f, 0x58 }, |
| { 0x10007970, 0x6f }, |
| { 0x10007971, 0xf0 }, |
| { 0x10007972, 0x5f }, |
| { 0x10007973, 0xf3 }, |
| { 0x10007974, 0x13 }, |
| { 0x10007975, 0x01 }, |
| { 0x10007976, 0x01 }, |
| { 0x10007977, 0xfe }, |
| { 0x10007978, 0x23 }, |
| { 0x10007979, 0x2c }, |
| { 0x1000797a, 0x81 }, |
| { 0x1000797b, 0x00 }, |
| { 0x1000797c, 0x83 }, |
| { 0x1000797d, 0xc7 }, |
| { 0x1000797e, 0x21 }, |
| { 0x1000797f, 0x41 }, |
| { 0x10007980, 0x23 }, |
| { 0x10007981, 0x2e }, |
| { 0x10007982, 0x11 }, |
| { 0x10007983, 0x00 }, |
| { 0x10007984, 0x23 }, |
| { 0x10007985, 0x2a }, |
| { 0x10007986, 0x91 }, |
| { 0x10007987, 0x00 }, |
| { 0x10007988, 0x23 }, |
| { 0x10007989, 0x28 }, |
| { 0x1000798a, 0x21 }, |
| { 0x1000798b, 0x01 }, |
| { 0x1000798c, 0x23 }, |
| { 0x1000798d, 0x26 }, |
| { 0x1000798e, 0x31 }, |
| { 0x1000798f, 0x01 }, |
| { 0x10007990, 0x13 }, |
| { 0x10007991, 0x07 }, |
| { 0x10007992, 0x10 }, |
| { 0x10007993, 0x00 }, |
| { 0x10007994, 0x63 }, |
| { 0x10007995, 0x92 }, |
| { 0x10007996, 0xe7 }, |
| { 0x10007997, 0x02 }, |
| { 0x10007998, 0xa3 }, |
| { 0x10007999, 0x81 }, |
| { 0x1000799a, 0xf1 }, |
| { 0x1000799b, 0x40 }, |
| { 0x1000799c, 0x83 }, |
| { 0x1000799d, 0x20 }, |
| { 0x1000799e, 0xc1 }, |
| { 0x1000799f, 0x01 }, |
| { 0x100079a0, 0x03 }, |
| { 0x100079a1, 0x24 }, |
| { 0x100079a2, 0x81 }, |
| { 0x100079a3, 0x01 }, |
| { 0x100079a4, 0x83 }, |
| { 0x100079a5, 0x24 }, |
| { 0x100079a6, 0x41 }, |
| { 0x100079a7, 0x01 }, |
| { 0x100079a8, 0x03 }, |
| { 0x100079a9, 0x29 }, |
| { 0x100079aa, 0x01 }, |
| { 0x100079ab, 0x01 }, |
| { 0x100079ac, 0x83 }, |
| { 0x100079ad, 0x29 }, |
| { 0x100079ae, 0xc1 }, |
| { 0x100079af, 0x00 }, |
| { 0x100079b0, 0x13 }, |
| { 0x100079b1, 0x01 }, |
| { 0x100079b2, 0x01 }, |
| { 0x100079b3, 0x02 }, |
| { 0x100079b4, 0x67 }, |
| { 0x100079b5, 0x80 }, |
| { 0x100079b6, 0x00 }, |
| { 0x100079b7, 0x00 }, |
| { 0x100079b8, 0xe3 }, |
| { 0x100079b9, 0x92 }, |
| { 0x100079ba, 0x07 }, |
| { 0x100079bb, 0xfe }, |
| { 0x100079bc, 0x37 }, |
| { 0x100079bd, 0xc9 }, |
| { 0x100079be, 0x00 }, |
| { 0x100079bf, 0x00 }, |
| { 0x100079c0, 0x83 }, |
| { 0x100079c1, 0x47 }, |
| { 0x100079c2, 0x09 }, |
| { 0x100079c3, 0x56 }, |
| { 0x100079c4, 0x13 }, |
| { 0x100079c5, 0x07 }, |
| { 0x100079c6, 0x80 }, |
| { 0x100079c7, 0x01 }, |
| { 0x100079c8, 0x93 }, |
| { 0x100079c9, 0xf7 }, |
| { 0x100079ca, 0xf7 }, |
| { 0x100079cb, 0x0f }, |
| { 0x100079cc, 0xe3 }, |
| { 0x100079cd, 0x78 }, |
| { 0x100079ce, 0xf7 }, |
| { 0x100079cf, 0xfc }, |
| { 0x100079d0, 0x83 }, |
| { 0x100079d1, 0xc7 }, |
| { 0x100079d2, 0x31 }, |
| { 0x100079d3, 0x40 }, |
| { 0x100079d4, 0xe3 }, |
| { 0x100079d5, 0x84 }, |
| { 0x100079d6, 0x07 }, |
| { 0x100079d7, 0xfc }, |
| { 0x100079d8, 0xb7 }, |
| { 0x100079d9, 0xd4 }, |
| { 0x100079da, 0x00 }, |
| { 0x100079db, 0x00 }, |
| { 0x100079dc, 0x03 }, |
| { 0x100079dd, 0xc5 }, |
| { 0x100079de, 0x94 }, |
| { 0x100079df, 0x47 }, |
| { 0x100079e0, 0xb7 }, |
| { 0x100079e1, 0x15 }, |
| { 0x100079e2, 0x00 }, |
| { 0x100079e3, 0x00 }, |
| { 0x100079e4, 0x93 }, |
| { 0x100079e5, 0x85 }, |
| { 0x100079e6, 0x85 }, |
| { 0x100079e7, 0x38 }, |
| { 0x100079e8, 0x13 }, |
| { 0x100079e9, 0x75 }, |
| { 0x100079ea, 0xf5 }, |
| { 0x100079eb, 0x0f }, |
| { 0x100079ec, 0xef }, |
| { 0x100079ed, 0xe0 }, |
| { 0x100079ee, 0x5f }, |
| { 0x100079ef, 0xe0 }, |
| { 0x100079f0, 0x93 }, |
| { 0x100079f1, 0x55 }, |
| { 0x100079f2, 0xf5 }, |
| { 0x100079f3, 0x41 }, |
| { 0x100079f4, 0xef }, |
| { 0x100079f5, 0xe0 }, |
| { 0x100079f6, 0x0f }, |
| { 0x100079f7, 0x83 }, |
| { 0x100079f8, 0xa3 }, |
| { 0x100079f9, 0x81 }, |
| { 0x100079fa, 0x01 }, |
| { 0x100079fb, 0x40 }, |
| { 0x100079fc, 0x83 }, |
| { 0x100079fd, 0x27 }, |
| { 0x100079fe, 0xc9 }, |
| { 0x100079ff, 0x5f }, |
| { 0x10007a00, 0x37 }, |
| { 0x10007a01, 0x07 }, |
| { 0x10007a02, 0x00 }, |
| { 0x10007a03, 0x02 }, |
| { 0x10007a04, 0xb3 }, |
| { 0x10007a05, 0xf7 }, |
| { 0x10007a06, 0xe7 }, |
| { 0x10007a07, 0x00 }, |
| { 0x10007a08, 0xe3 }, |
| { 0x10007a09, 0x8a }, |
| { 0x10007a0a, 0x07 }, |
| { 0x10007a0b, 0xf8 }, |
| { 0x10007a0c, 0x03 }, |
| { 0x10007a0d, 0xc7 }, |
| { 0x10007a0e, 0x04 }, |
| { 0x10007a0f, 0x90 }, |
| { 0x10007a10, 0x93 }, |
| { 0x10007a11, 0x07 }, |
| { 0x10007a12, 0x10 }, |
| { 0x10007a13, 0x00 }, |
| { 0x10007a14, 0x13 }, |
| { 0x10007a15, 0x77 }, |
| { 0x10007a16, 0x17 }, |
| { 0x10007a17, 0x00 }, |
| { 0x10007a18, 0x63 }, |
| { 0x10007a19, 0x1c }, |
| { 0x10007a1a, 0x07 }, |
| { 0x10007a1b, 0x00 }, |
| { 0x10007a1c, 0x83 }, |
| { 0x10007a1d, 0xc7 }, |
| { 0x10007a1e, 0x34 }, |
| { 0x10007a1f, 0x54 }, |
| { 0x10007a20, 0x93 }, |
| { 0x10007a21, 0xf7 }, |
| { 0x10007a22, 0xf7 }, |
| { 0x10007a23, 0x0f }, |
| { 0x10007a24, 0x93 }, |
| { 0x10007a25, 0xd7 }, |
| { 0x10007a26, 0x17 }, |
| { 0x10007a27, 0x00 }, |
| { 0x10007a28, 0x93 }, |
| { 0x10007a29, 0xc7 }, |
| { 0x10007a2a, 0x17 }, |
| { 0x10007a2b, 0x00 }, |
| { 0x10007a2c, 0x93 }, |
| { 0x10007a2d, 0xf7 }, |
| { 0x10007a2e, 0x17 }, |
| { 0x10007a2f, 0x00 }, |
| { 0x10007a30, 0xa3 }, |
| { 0x10007a31, 0x85 }, |
| { 0x10007a32, 0xf1 }, |
| { 0x10007a33, 0x42 }, |
| { 0x10007a34, 0x37 }, |
| { 0x10007a35, 0xd6 }, |
| { 0x10007a36, 0x00 }, |
| { 0x10007a37, 0x00 }, |
| { 0x10007a38, 0x03 }, |
| { 0x10007a39, 0x47 }, |
| { 0x10007a3a, 0x06 }, |
| { 0x10007a3b, 0x90 }, |
| { 0x10007a3c, 0x93 }, |
| { 0x10007a3d, 0x06 }, |
| { 0x10007a3e, 0x10 }, |
| { 0x10007a3f, 0x00 }, |
| { 0x10007a40, 0x13 }, |
| { 0x10007a41, 0x77 }, |
| { 0x10007a42, 0x27 }, |
| { 0x10007a43, 0x00 }, |
| { 0x10007a44, 0x63 }, |
| { 0x10007a45, 0x18 }, |
| { 0x10007a46, 0x07 }, |
| { 0x10007a47, 0x00 }, |
| { 0x10007a48, 0x03 }, |
| { 0x10007a49, 0x47 }, |
| { 0x10007a4a, 0x36 }, |
| { 0x10007a4b, 0x54 }, |
| { 0x10007a4c, 0x13 }, |
| { 0x10007a4d, 0x77 }, |
| { 0x10007a4e, 0x17 }, |
| { 0x10007a4f, 0x00 }, |
| { 0x10007a50, 0xb3 }, |
| { 0x10007a51, 0x86 }, |
| { 0x10007a52, 0xe6 }, |
| { 0x10007a53, 0x40 }, |
| { 0x10007a54, 0x23 }, |
| { 0x10007a55, 0x85 }, |
| { 0x10007a56, 0xd1 }, |
| { 0x10007a57, 0x42 }, |
| { 0x10007a58, 0xb7 }, |
| { 0x10007a59, 0xd5 }, |
| { 0x10007a5a, 0x00 }, |
| { 0x10007a5b, 0x00 }, |
| { 0x10007a5c, 0x03 }, |
| { 0x10007a5d, 0xc6 }, |
| { 0x10007a5e, 0x05 }, |
| { 0x10007a5f, 0x92 }, |
| { 0x10007a60, 0x13 }, |
| { 0x10007a61, 0x07 }, |
| { 0x10007a62, 0x10 }, |
| { 0x10007a63, 0x00 }, |
| { 0x10007a64, 0x13 }, |
| { 0x10007a65, 0x76 }, |
| { 0x10007a66, 0x16 }, |
| { 0x10007a67, 0x00 }, |
| { 0x10007a68, 0x63 }, |
| { 0x10007a69, 0x1c }, |
| { 0x10007a6a, 0x06 }, |
| { 0x10007a6b, 0x00 }, |
| { 0x10007a6c, 0x03 }, |
| { 0x10007a6d, 0xc7 }, |
| { 0x10007a6e, 0x35 }, |
| { 0x10007a6f, 0x54 }, |
| { 0x10007a70, 0x13 }, |
| { 0x10007a71, 0x77 }, |
| { 0x10007a72, 0xf7 }, |
| { 0x10007a73, 0x0f }, |
| { 0x10007a74, 0x13 }, |
| { 0x10007a75, 0x57 }, |
| { 0x10007a76, 0x37 }, |
| { 0x10007a77, 0x00 }, |
| { 0x10007a78, 0x13 }, |
| { 0x10007a79, 0x47 }, |
| { 0x10007a7a, 0x17 }, |
| { 0x10007a7b, 0x00 }, |
| { 0x10007a7c, 0x13 }, |
| { 0x10007a7d, 0x77 }, |
| { 0x10007a7e, 0x17 }, |
| { 0x10007a7f, 0x00 }, |
| { 0x10007a80, 0xa3 }, |
| { 0x10007a81, 0x84 }, |
| { 0x10007a82, 0xe1 }, |
| { 0x10007a83, 0x42 }, |
| { 0x10007a84, 0xb7 }, |
| { 0x10007a85, 0xd5 }, |
| { 0x10007a86, 0x00 }, |
| { 0x10007a87, 0x00 }, |
| { 0x10007a88, 0x03 }, |
| { 0x10007a89, 0xc6 }, |
| { 0x10007a8a, 0x05 }, |
| { 0x10007a8b, 0x92 }, |
| { 0x10007a8c, 0x13 }, |
| { 0x10007a8d, 0x07 }, |
| { 0x10007a8e, 0x10 }, |
| { 0x10007a8f, 0x00 }, |
| { 0x10007a90, 0x13 }, |
| { 0x10007a91, 0x76 }, |
| { 0x10007a92, 0x26 }, |
| { 0x10007a93, 0x00 }, |
| { 0x10007a94, 0x63 }, |
| { 0x10007a95, 0x1c }, |
| { 0x10007a96, 0x06 }, |
| { 0x10007a97, 0x00 }, |
| { 0x10007a98, 0x03 }, |
| { 0x10007a99, 0xc7 }, |
| { 0x10007a9a, 0x35 }, |
| { 0x10007a9b, 0x54 }, |
| { 0x10007a9c, 0x13 }, |
| { 0x10007a9d, 0x77 }, |
| { 0x10007a9e, 0xf7 }, |
| { 0x10007a9f, 0x0f }, |
| { 0x10007aa0, 0x13 }, |
| { 0x10007aa1, 0x57 }, |
| { 0x10007aa2, 0x27 }, |
| { 0x10007aa3, 0x00 }, |
| { 0x10007aa4, 0x13 }, |
| { 0x10007aa5, 0x47 }, |
| { 0x10007aa6, 0x17 }, |
| { 0x10007aa7, 0x00 }, |
| { 0x10007aa8, 0x13 }, |
| { 0x10007aa9, 0x77 }, |
| { 0x10007aaa, 0x17 }, |
| { 0x10007aab, 0x00 }, |
| { 0x10007aac, 0x23 }, |
| { 0x10007aad, 0x84 }, |
| { 0x10007aae, 0xe1 }, |
| { 0x10007aaf, 0x42 }, |
| { 0x10007ab0, 0x63 }, |
| { 0x10007ab1, 0x84 }, |
| { 0x10007ab2, 0x07 }, |
| { 0x10007ab3, 0x00 }, |
| { 0x10007ab4, 0xe3 }, |
| { 0x10007ab5, 0x94 }, |
| { 0x10007ab6, 0x06 }, |
| { 0x10007ab7, 0xee }, |
| { 0x10007ab8, 0xef }, |
| { 0x10007ab9, 0x90 }, |
| { 0x10007aba, 0x0f }, |
| { 0x10007abb, 0x86 }, |
| { 0x10007abc, 0xef }, |
| { 0x10007abd, 0xd0 }, |
| { 0x10007abe, 0x0f }, |
| { 0x10007abf, 0x97 }, |
| { 0x10007ac0, 0x37 }, |
| { 0x10007ac1, 0x15 }, |
| { 0x10007ac2, 0x00 }, |
| { 0x10007ac3, 0x00 }, |
| { 0x10007ac4, 0x13 }, |
| { 0x10007ac5, 0x05 }, |
| { 0x10007ac6, 0x85 }, |
| { 0x10007ac7, 0xbb }, |
| { 0x10007ac8, 0x93 }, |
| { 0x10007ac9, 0x05 }, |
| { 0x10007aca, 0x00 }, |
| { 0x10007acb, 0x00 }, |
| { 0x10007acc, 0xef }, |
| { 0x10007acd, 0xd0 }, |
| { 0x10007ace, 0x9f }, |
| { 0x10007acf, 0xf5 }, |
| { 0x10007ad0, 0xb7 }, |
| { 0x10007ad1, 0xd7 }, |
| { 0x10007ad2, 0x00 }, |
| { 0x10007ad3, 0x00 }, |
| { 0x10007ad4, 0x83 }, |
| { 0x10007ad5, 0xc7 }, |
| { 0x10007ad6, 0x07 }, |
| { 0x10007ad7, 0x47 }, |
| { 0x10007ad8, 0x93 }, |
| { 0x10007ad9, 0xf7 }, |
| { 0x10007ada, 0x47 }, |
| { 0x10007adb, 0x00 }, |
| { 0x10007adc, 0xe3 }, |
| { 0x10007add, 0x80 }, |
| { 0x10007ade, 0x07 }, |
| { 0x10007adf, 0xec }, |
| { 0x10007ae0, 0xef }, |
| { 0x10007ae1, 0x80 }, |
| { 0x10007ae2, 0xdf }, |
| { 0x10007ae3, 0xf4 }, |
| { 0x10007ae4, 0x23 }, |
| { 0x10007ae5, 0x89 }, |
| { 0x10007ae6, 0xa1 }, |
| { 0x10007ae7, 0x40 }, |
| { 0x10007ae8, 0x6f }, |
| { 0x10007ae9, 0xf0 }, |
| { 0x10007aea, 0x5f }, |
| { 0x10007aeb, 0xeb }, |
| { 0x10007aec, 0x00 }, |
| { 0x10007aed, 0x00 }, |
| { 0x10007aee, 0x00 }, |
| { 0x10007aef, 0x00 }, |
| { 0x3fc2bf83, 0x00 }, |
| { 0x3fc2bf82, 0x00 }, |
| { 0x3fc2bf81, 0x00 }, |
| { 0x3fc2bf80, 0x00 }, |
| { 0x3fc2bfc7, 0x00 }, |
| { 0x3fc2bfc6, 0x00 }, |
| { 0x3fc2bfc5, 0x00 }, |
| { 0x3fc2bfc4, 0x00 }, |
| { 0x3fc2bfc3, 0x00 }, |
| { 0x3fc2bfc2, 0x00 }, |
| { 0x3fc2bfc1, 0x00 }, |
| { 0x3fc2bfc0, 0x03 }, |
| { 0x0000d486, 0x43 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 }, |
| { 0x1000db00, 0x04 }, |
| { 0x1000db01, 0x00 }, |
| { 0x1000db02, 0x11 }, |
| { 0x1000db03, 0x00 }, |
| { 0x1000db04, 0x00 }, |
| { 0x1000db05, 0x82 }, |
| { 0x1000db06, 0x04 }, |
| { 0x1000db07, 0xf1 }, |
| { 0x1000db08, 0x00 }, |
| { 0x1000db09, 0x00 }, |
| { 0x1000db0a, 0x40 }, |
| { 0x1000db0b, 0x02 }, |
| { 0x1000db0c, 0xf2 }, |
| { 0x1000db0d, 0x00 }, |
| { 0x1000db0e, 0x00 }, |
| { 0x1000db0f, 0xe0 }, |
| { 0x1000db10, 0x00 }, |
| { 0x1000db11, 0x10 }, |
| { 0x1000db12, 0x00 }, |
| { 0x1000db13, 0x00 }, |
| { 0x1000db14, 0x45 }, |
| { 0x0000d540, 0x01 }, |
| { 0x0000c081, 0xfc }, |
| { 0x0000f01e, 0x80 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, |
| }; |
| |
| /* |
| * The 'patch code' is written to the patch code area. |
| * The patch code area is used for SDCA register expansion flexibility. |
| */ |
| static const struct reg_sequence rt1320_patch_code_write[] = { |
| { 0x10007000, 0x37 }, |
| { 0x10007001, 0x77 }, |
| { 0x10007002, 0x00 }, |
| { 0x10007003, 0x10 }, |
| { 0x10007004, 0xb7 }, |
| { 0x10007005, 0xe7 }, |
| { 0x10007006, 0x00 }, |
| { 0x10007007, 0x10 }, |
| { 0x10007008, 0x13 }, |
| { 0x10007009, 0x07 }, |
| { 0x1000700a, 0x07 }, |
| { 0x1000700b, 0x40 }, |
| { 0x1000700c, 0x23 }, |
| { 0x1000700d, 0xae }, |
| { 0x1000700e, 0xe7 }, |
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| { 0x100077d6, 0xf4 }, |
| { 0x100077d7, 0x58 }, |
| { 0x100077d8, 0x03 }, |
| { 0x100077d9, 0x45 }, |
| { 0x100077da, 0x64 }, |
| { 0x100077db, 0xd9 }, |
| { 0x100077dc, 0xb7 }, |
| { 0x100077dd, 0x15 }, |
| { 0x100077de, 0x00 }, |
| { 0x100077df, 0x00 }, |
| { 0x100077e0, 0x93 }, |
| { 0x100077e1, 0x85 }, |
| { 0x100077e2, 0x85 }, |
| { 0x100077e3, 0x38 }, |
| { 0x100077e4, 0x13 }, |
| { 0x100077e5, 0x75 }, |
| { 0x100077e6, 0xf5 }, |
| { 0x100077e7, 0x0f }, |
| { 0x100077e8, 0xef }, |
| { 0x100077e9, 0xe0 }, |
| { 0x100077ea, 0x9f }, |
| { 0x100077eb, 0xd0 }, |
| { 0x100077ec, 0x93 }, |
| { 0x100077ed, 0x55 }, |
| { 0x100077ee, 0xf5 }, |
| { 0x100077ef, 0x41 }, |
| { 0x100077f0, 0xef }, |
| { 0x100077f1, 0xe0 }, |
| { 0x100077f2, 0x8f }, |
| { 0x100077f3, 0xa3 }, |
| { 0x100077f4, 0x23 }, |
| { 0x100077f5, 0x82 }, |
| { 0x100077f6, 0x04 }, |
| { 0x100077f7, 0x58 }, |
| { 0x100077f8, 0xa3 }, |
| { 0x100077f9, 0x0a }, |
| { 0x100077fa, 0x04 }, |
| { 0x100077fb, 0xd8 }, |
| { 0x100077fc, 0x83 }, |
| { 0x100077fd, 0x20 }, |
| { 0x100077fe, 0xc1 }, |
| { 0x100077ff, 0x00 }, |
| { 0x10007800, 0x03 }, |
| { 0x10007801, 0x24 }, |
| { 0x10007802, 0x81 }, |
| { 0x10007803, 0x00 }, |
| { 0x10007804, 0x83 }, |
| { 0x10007805, 0x24 }, |
| { 0x10007806, 0x41 }, |
| { 0x10007807, 0x00 }, |
| { 0x10007808, 0x13 }, |
| { 0x10007809, 0x01 }, |
| { 0x1000780a, 0x01 }, |
| { 0x1000780b, 0x01 }, |
| { 0x1000780c, 0x67 }, |
| { 0x1000780d, 0x80 }, |
| { 0x1000780e, 0x00 }, |
| { 0x1000780f, 0x00 }, |
| { 0x10007810, 0x67 }, |
| { 0x10007811, 0x80 }, |
| { 0x10007812, 0x00 }, |
| { 0x10007813, 0x00 }, |
| { 0x10007814, 0x13 }, |
| { 0x10007815, 0x01 }, |
| { 0x10007816, 0x01 }, |
| { 0x10007817, 0xff }, |
| { 0x10007818, 0x23 }, |
| { 0x10007819, 0x26 }, |
| { 0x1000781a, 0x11 }, |
| { 0x1000781b, 0x00 }, |
| { 0x1000781c, 0xef }, |
| { 0x1000781d, 0xd0 }, |
| { 0x1000781e, 0x8f }, |
| { 0x1000781f, 0x86 }, |
| { 0x10007820, 0x83 }, |
| { 0x10007821, 0xc7 }, |
| { 0x10007822, 0x11 }, |
| { 0x10007823, 0x42 }, |
| { 0x10007824, 0x63 }, |
| { 0x10007825, 0x86 }, |
| { 0x10007826, 0x07 }, |
| { 0x10007827, 0x00 }, |
| { 0x10007828, 0x03 }, |
| { 0x10007829, 0xc7 }, |
| { 0x1000782a, 0x01 }, |
| { 0x1000782b, 0x42 }, |
| { 0x1000782c, 0x63 }, |
| { 0x1000782d, 0x10 }, |
| { 0x1000782e, 0x07 }, |
| { 0x1000782f, 0x02 }, |
| { 0x10007830, 0x83 }, |
| { 0x10007831, 0xc6 }, |
| { 0x10007832, 0x21 }, |
| { 0x10007833, 0x41 }, |
| { 0x10007834, 0x13 }, |
| { 0x10007835, 0x07 }, |
| { 0x10007836, 0xf0 }, |
| { 0x10007837, 0x01 }, |
| { 0x10007838, 0x13 }, |
| { 0x10007839, 0x05 }, |
| { 0x1000783a, 0xf0 }, |
| { 0x1000783b, 0x01 }, |
| { 0x1000783c, 0x63 }, |
| { 0x1000783d, 0x98 }, |
| { 0x1000783e, 0xe6 }, |
| { 0x1000783f, 0x02 }, |
| { 0x10007840, 0x63 }, |
| { 0x10007841, 0x8a }, |
| { 0x10007842, 0x07 }, |
| { 0x10007843, 0x02 }, |
| { 0x10007844, 0x83 }, |
| { 0x10007845, 0xc7 }, |
| { 0x10007846, 0x01 }, |
| { 0x10007847, 0x42 }, |
| { 0x10007848, 0x63 }, |
| { 0x10007849, 0x86 }, |
| { 0x1000784a, 0x07 }, |
| { 0x1000784b, 0x02 }, |
| { 0x1000784c, 0x83 }, |
| { 0x1000784d, 0xc7 }, |
| { 0x1000784e, 0x31 }, |
| { 0x1000784f, 0x42 }, |
| { 0x10007850, 0x63 }, |
| { 0x10007851, 0x86 }, |
| { 0x10007852, 0x07 }, |
| { 0x10007853, 0x00 }, |
| { 0x10007854, 0x83 }, |
| { 0x10007855, 0xc7 }, |
| { 0x10007856, 0x21 }, |
| { 0x10007857, 0x42 }, |
| { 0x10007858, 0x63 }, |
| { 0x10007859, 0x9e }, |
| { 0x1000785a, 0x07 }, |
| { 0x1000785b, 0x00 }, |
| { 0x1000785c, 0x03 }, |
| { 0x1000785d, 0xc7 }, |
| { 0x1000785e, 0x21 }, |
| { 0x1000785f, 0x41 }, |
| { 0x10007860, 0x93 }, |
| { 0x10007861, 0x07 }, |
| { 0x10007862, 0xb0 }, |
| { 0x10007863, 0x01 }, |
| { 0x10007864, 0x63 }, |
| { 0x10007865, 0x08 }, |
| { 0x10007866, 0xf7 }, |
| { 0x10007867, 0x00 }, |
| { 0x10007868, 0x13 }, |
| { 0x10007869, 0x05 }, |
| { 0x1000786a, 0xb0 }, |
| { 0x1000786b, 0x01 }, |
| { 0x1000786c, 0xef }, |
| { 0x1000786d, 0xd0 }, |
| { 0x1000786e, 0x0f }, |
| { 0x1000786f, 0xcf }, |
| { 0x10007870, 0xef }, |
| { 0x10007871, 0xd0 }, |
| { 0x10007872, 0x8f }, |
| { 0x10007873, 0xa4 }, |
| { 0x10007874, 0x93 }, |
| { 0x10007875, 0x06 }, |
| { 0x10007876, 0x10 }, |
| { 0x10007877, 0x00 }, |
| { 0x10007878, 0xa3 }, |
| { 0x10007879, 0x89 }, |
| { 0x1000787a, 0xd1 }, |
| { 0x1000787b, 0x40 }, |
| { 0x1000787c, 0x37 }, |
| { 0x1000787d, 0xd7 }, |
| { 0x1000787e, 0x00 }, |
| { 0x1000787f, 0x10 }, |
| { 0x10007880, 0x83 }, |
| { 0x10007881, 0x47 }, |
| { 0x10007882, 0x07 }, |
| { 0x10007883, 0xd9 }, |
| { 0x10007884, 0x93 }, |
| { 0x10007885, 0xf7 }, |
| { 0x10007886, 0xf7 }, |
| { 0x10007887, 0x0f }, |
| { 0x10007888, 0x63 }, |
| { 0x10007889, 0x90 }, |
| { 0x1000788a, 0x07 }, |
| { 0x1000788b, 0x02 }, |
| { 0x1000788c, 0x37 }, |
| { 0x1000788d, 0xc6 }, |
| { 0x1000788e, 0x00 }, |
| { 0x1000788f, 0x00 }, |
| { 0x10007890, 0x83 }, |
| { 0x10007891, 0x47 }, |
| { 0x10007892, 0x26 }, |
| { 0x10007893, 0x04 }, |
| { 0x10007894, 0x93 }, |
| { 0x10007895, 0xe7 }, |
| { 0x10007896, 0x07 }, |
| { 0x10007897, 0xf8 }, |
| { 0x10007898, 0x93 }, |
| { 0x10007899, 0xf7 }, |
| { 0x1000789a, 0xf7 }, |
| { 0x1000789b, 0x0f }, |
| { 0x1000789c, 0x23 }, |
| { 0x1000789d, 0x01 }, |
| { 0x1000789e, 0xf6 }, |
| { 0x1000789f, 0x04 }, |
| { 0x100078a0, 0x23 }, |
| { 0x100078a1, 0x08 }, |
| { 0x100078a2, 0xd7 }, |
| { 0x100078a3, 0xd8 }, |
| { 0x100078a4, 0x23 }, |
| { 0x100078a5, 0x09 }, |
| { 0x100078a6, 0x07 }, |
| { 0x100078a7, 0xd8 }, |
| { 0x100078a8, 0x83 }, |
| { 0x100078a9, 0x20 }, |
| { 0x100078aa, 0xc1 }, |
| { 0x100078ab, 0x00 }, |
| { 0x100078ac, 0x13 }, |
| { 0x100078ad, 0x01 }, |
| { 0x100078ae, 0x01 }, |
| { 0x100078af, 0x01 }, |
| { 0x100078b0, 0x67 }, |
| { 0x100078b1, 0x80 }, |
| { 0x100078b2, 0x00 }, |
| { 0x100078b3, 0x00 }, |
| { 0x3fc2bfc7, 0x00 }, |
| { 0x3fc2bfc6, 0x00 }, |
| { 0x3fc2bfc5, 0x00 }, |
| { 0x3fc2bfc4, 0x01 }, |
| { 0x0000d486, 0x43 }, |
| { 0x1000db00, 0x02 }, |
| { 0x1000db01, 0x00 }, |
| { 0x1000db02, 0x11 }, |
| { 0x1000db03, 0x00 }, |
| { 0x1000db04, 0x00 }, |
| { 0x1000db05, 0x82 }, |
| { 0x1000db06, 0x04 }, |
| { 0x1000db07, 0xf1 }, |
| { 0x1000db08, 0x00 }, |
| { 0x1000db09, 0x00 }, |
| { 0x1000db0a, 0x40 }, |
| { 0x0000d540, 0x01 }, |
| }; |
| |
| static const struct reg_default rt1320_reg_defaults[] = { |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 }, |
| }; |
| |
| static const struct reg_default rt1320_mbq_defaults[] = { |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 }, |
| { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 }, |
| }; |
| |
| static bool rt1320_readable_register(struct device *dev, unsigned int reg) |
| { |
| switch (reg) { |
| case 0xc000 ... 0xc086: |
| case 0xc400 ... 0xc409: |
| case 0xc480 ... 0xc48f: |
| case 0xc4c0 ... 0xc4c4: |
| case 0xc4e0 ... 0xc4e7: |
| case 0xc500: |
| case 0xc560 ... 0xc56b: |
| case 0xc570: |
| case 0xc580 ... 0xc59a: |
| case 0xc5b0 ... 0xc60f: |
| case 0xc640 ... 0xc64f: |
| case 0xc670: |
| case 0xc680 ... 0xc683: |
| case 0xc700 ... 0xc76f: |
| case 0xc800 ... 0xc801: |
| case 0xc820: |
| case 0xc900 ... 0xc901: |
| case 0xc920 ... 0xc921: |
| case 0xca00 ... 0xca07: |
| case 0xca20 ... 0xca27: |
| case 0xca40 ... 0xca4b: |
| case 0xca60 ... 0xca68: |
| case 0xca80 ... 0xca88: |
| case 0xcb00 ... 0xcb0c: |
| case 0xcc00 ... 0xcc12: |
| case 0xcc80 ... 0xcc81: |
| case 0xcd00: |
| case 0xcd80 ... 0xcd82: |
| case 0xce00 ... 0xce4d: |
| case 0xcf00 ... 0xcf25: |
| case 0xd000 ... 0xd0ff: |
| case 0xd100 ... 0xd1ff: |
| case 0xd200 ... 0xd2ff: |
| case 0xd300 ... 0xd3ff: |
| case 0xd400 ... 0xd403: |
| case 0xd410 ... 0xd417: |
| case 0xd470 ... 0xd497: |
| case 0xd4dc ... 0xd50f: |
| case 0xd520 ... 0xd543: |
| case 0xd560 ... 0xd5ef: |
| case 0xd600 ... 0xd663: |
| case 0xda00 ... 0xda6e: |
| case 0xda80 ... 0xda9e: |
| case 0xdb00 ... 0xdb7f: |
| case 0xdc00: |
| case 0xdc20 ... 0xdc21: |
| case 0xdd00 ... 0xdd17: |
| case 0xde00 ... 0xde09: |
| case 0xdf00 ... 0xdf1b: |
| case 0xe000 ... 0xe847: |
| case 0xf01e: |
| case 0xf717 ... 0xf719: |
| case 0xf720 ... 0xf723: |
| case 0x1000cd91 ... 0x1000cd96: |
| case 0x1000f008: |
| case 0x1000f021: |
| case 0x3fe2e000 ... 0x3fe2e003: |
| case 0x3fc2ab80 ... 0x3fc2abd4: |
| /* 0x41000189/0x4100018a */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01): |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02): |
| /* 0x41001388 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): |
| /* 0x41001988 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0): |
| /* 0x41080000 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): |
| /* 0x41080200 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0): |
| /* 0x41080900 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): |
| /* 0x41080980 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): |
| /* 0x41081080 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): |
| /* 0x41081480/0x41081488 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): |
| /* 0x41081980 */ |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| static bool rt1320_volatile_register(struct device *dev, unsigned int reg) |
| { |
| switch (reg) { |
| case 0xc000: |
| case 0xc003: |
| case 0xc081: |
| case 0xc402 ... 0xc406: |
| case 0xc48c ... 0xc48f: |
| case 0xc560: |
| case 0xc5b5 ... 0xc5b7: |
| case 0xc5fc ... 0xc5ff: |
| case 0xc820: |
| case 0xc900: |
| case 0xc920: |
| case 0xca42: |
| case 0xca62: |
| case 0xca82: |
| case 0xcd00: |
| case 0xce03: |
| case 0xce10: |
| case 0xce14 ... 0xce17: |
| case 0xce44 ... 0xce49: |
| case 0xce4c ... 0xce4d: |
| case 0xcf0c: |
| case 0xcf10 ... 0xcf25: |
| case 0xd486 ... 0xd487: |
| case 0xd4e5 ... 0xd4e6: |
| case 0xd4e8 ... 0xd4ff: |
| case 0xd530: |
| case 0xd540: |
| case 0xd543: |
| case 0xdb58 ... 0xdb5f: |
| case 0xdb60 ... 0xdb63: |
| case 0xdb68 ... 0xdb69: |
| case 0xdb6d: |
| case 0xdb70 ... 0xdb71: |
| case 0xdb76: |
| case 0xdb7a: |
| case 0xdb7c ... 0xdb7f: |
| case 0xdd0c ... 0xdd13: |
| case 0xde02: |
| case 0xdf14 ... 0xdf1b: |
| case 0xe83c ... 0xe847: |
| case 0xf01e: |
| case 0xf717 ... 0xf719: |
| case 0xf720 ... 0xf723: |
| case 0x10000000 ... 0x10007fff: |
| case 0x1000c000 ... 0x1000dfff: |
| case 0x1000f008: |
| case 0x1000f021: |
| case 0x3fc2ab80 ... 0x3fc2abd4: |
| case 0x3fc2bf80 ... 0x3fc2bf83: |
| case 0x3fc2bfc0 ... 0x3fc2bfc7: |
| case 0x3fe2e000 ... 0x3fe2e003: |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0): |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0): |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0): |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0): |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg) |
| { |
| switch (reg) { |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01): |
| case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02): |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| static const struct regmap_config rt1320_sdw_regmap = { |
| .reg_bits = 32, |
| .val_bits = 8, |
| .readable_reg = rt1320_readable_register, |
| .volatile_reg = rt1320_volatile_register, |
| .max_register = 0x41081980, |
| .reg_defaults = rt1320_reg_defaults, |
| .num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults), |
| .cache_type = REGCACHE_MAPLE, |
| .use_single_read = true, |
| .use_single_write = true, |
| }; |
| |
| static const struct regmap_config rt1320_mbq_regmap = { |
| .name = "sdw-mbq", |
| .reg_bits = 32, |
| .val_bits = 16, |
| .readable_reg = rt1320_mbq_readable_register, |
| .max_register = 0x41000192, |
| .reg_defaults = rt1320_mbq_defaults, |
| .num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults), |
| .cache_type = REGCACHE_MAPLE, |
| .use_single_read = true, |
| .use_single_write = true, |
| }; |
| |
| static int rt1320_read_prop(struct sdw_slave *slave) |
| { |
| struct sdw_slave_prop *prop = &slave->prop; |
| int nval; |
| int i, j; |
| u32 bit; |
| unsigned long addr; |
| struct sdw_dpn_prop *dpn; |
| |
| /* |
| * Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping |
| */ |
| sdw_slave_read_prop(slave); |
| |
| prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; |
| prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; |
| |
| prop->paging_support = true; |
| prop->lane_control_support = true; |
| |
| /* first we need to allocate memory for set bits in port lists */ |
| prop->source_ports = BIT(4); |
| prop->sink_ports = BIT(1); |
| |
| nval = hweight32(prop->source_ports); |
| prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, |
| sizeof(*prop->src_dpn_prop), GFP_KERNEL); |
| if (!prop->src_dpn_prop) |
| return -ENOMEM; |
| |
| i = 0; |
| dpn = prop->src_dpn_prop; |
| addr = prop->source_ports; |
| for_each_set_bit(bit, &addr, 32) { |
| dpn[i].num = bit; |
| dpn[i].type = SDW_DPN_FULL; |
| dpn[i].simple_ch_prep_sm = true; |
| dpn[i].ch_prep_timeout = 10; |
| i++; |
| } |
| |
| /* do this again for sink now */ |
| nval = hweight32(prop->sink_ports); |
| prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, |
| sizeof(*prop->sink_dpn_prop), GFP_KERNEL); |
| if (!prop->sink_dpn_prop) |
| return -ENOMEM; |
| |
| j = 0; |
| dpn = prop->sink_dpn_prop; |
| addr = prop->sink_ports; |
| for_each_set_bit(bit, &addr, 32) { |
| dpn[j].num = bit; |
| dpn[j].type = SDW_DPN_FULL; |
| dpn[j].simple_ch_prep_sm = true; |
| dpn[j].ch_prep_timeout = 10; |
| j++; |
| } |
| |
| /* set the timeout values */ |
| prop->clk_stop_timeout = 64; |
| |
| return 0; |
| } |
| |
| static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char ps) |
| { |
| unsigned int delay = 1000, val; |
| |
| pm_runtime_mark_last_busy(&rt1320->sdw_slave->dev); |
| |
| /* waiting for Actual PDE becomes to PS0/PS3 */ |
| while (delay) { |
| regmap_read(rt1320->regmap, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, |
| RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); |
| if (val == ps) |
| break; |
| |
| usleep_range(1000, 1500); |
| delay--; |
| } |
| if (!delay) { |
| dev_warn(&rt1320->sdw_slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); |
| return -ETIMEDOUT; |
| } |
| |
| return 0; |
| } |
| |
| static void rt1320_vc_preset(struct rt1320_sdw_priv *rt1320) |
| { |
| struct sdw_slave *slave = rt1320->sdw_slave; |
| unsigned int i, reg, val, delay, retry, tmp; |
| |
| regmap_multi_reg_write(rt1320->regmap, rt1320_vc_blind_write, ARRAY_SIZE(rt1320_vc_blind_write)); |
| |
| for (i = 0; i < ARRAY_SIZE(rt1320_vc_patch_code_write); i++) { |
| reg = rt1320_vc_patch_code_write[i].reg; |
| val = rt1320_vc_patch_code_write[i].def; |
| delay = rt1320_vc_patch_code_write[i].delay_us; |
| |
| if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) && |
| (val == 0x00)) { |
| retry = 200; |
| while (retry) { |
| regmap_read(rt1320->regmap, RT1320_KR0_INT_READY, &tmp); |
| dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp); |
| if (tmp == 0x1f) |
| break; |
| usleep_range(1000, 1500); |
| retry--; |
| } |
| if (!retry) |
| dev_warn(&slave->dev, "%s MCU is NOT ready!", __func__); |
| } |
| regmap_write(rt1320->regmap, reg, val); |
| if (delay) |
| usleep_range(delay, delay + 1000); |
| } |
| } |
| |
| static int rt1320_io_init(struct device *dev, struct sdw_slave *slave) |
| { |
| struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); |
| unsigned int amp_func_status, val, tmp; |
| |
| if (rt1320->hw_init) |
| return 0; |
| |
| regcache_cache_only(rt1320->regmap, false); |
| regcache_cache_only(rt1320->mbq_regmap, false); |
| if (rt1320->first_hw_init) { |
| regcache_cache_bypass(rt1320->regmap, true); |
| regcache_cache_bypass(rt1320->mbq_regmap, true); |
| } else { |
| /* |
| * PM runtime status is marked as 'active' only when a Slave reports as Attached |
| */ |
| /* update count of parent 'active' children */ |
| pm_runtime_set_active(&slave->dev); |
| } |
| |
| pm_runtime_get_noresume(&slave->dev); |
| |
| if (rt1320->version_id < 0) { |
| regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val); |
| rt1320->version_id = val; |
| } |
| |
| regmap_read(rt1320->regmap, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status); |
| dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status); |
| |
| /* initialization write */ |
| if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION)) { |
| if (rt1320->version_id < RT1320_VC) { |
| regmap_multi_reg_write(rt1320->regmap, rt1320_blind_write, ARRAY_SIZE(rt1320_blind_write)); |
| regmap_multi_reg_write(rt1320->regmap, rt1320_patch_code_write, |
| ARRAY_SIZE(rt1320_patch_code_write)); |
| } else if (rt1320->version_id == RT1320_VC) { |
| rt1320_vc_preset(rt1320); |
| } |
| |
| regmap_write(rt1320->regmap, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), |
| FUNCTION_NEEDS_INITIALIZATION); |
| } |
| if (!rt1320->first_hw_init && rt1320->version_id == RT1320_VA) { |
| regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, |
| RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0); |
| regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val); |
| regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp); |
| val = (tmp << 8) | val; |
| regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp); |
| val = (tmp << 16) | val; |
| regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp); |
| val = (tmp << 24) | val; |
| dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val); |
| /* |
| * We call the version b which has the new DSP ROM code against version a. |
| * Therefore, we read the DSP address to check the ID. |
| */ |
| if (val == RT1320_VER_B_ID) |
| rt1320->version_id = RT1320_VB; |
| regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, |
| RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3); |
| } |
| dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id); |
| |
| if (rt1320->first_hw_init) { |
| regcache_cache_bypass(rt1320->regmap, false); |
| regcache_cache_bypass(rt1320->mbq_regmap, false); |
| regcache_mark_dirty(rt1320->regmap); |
| regcache_mark_dirty(rt1320->mbq_regmap); |
| } |
| |
| /* Mark Slave initialization complete */ |
| rt1320->first_hw_init = true; |
| rt1320->hw_init = true; |
| |
| pm_runtime_mark_last_busy(&slave->dev); |
| pm_runtime_put_autosuspend(&slave->dev); |
| |
| dev_dbg(&slave->dev, "%s hw_init complete\n", __func__); |
| return 0; |
| } |
| |
| static int rt1320_update_status(struct sdw_slave *slave, |
| enum sdw_slave_status status) |
| { |
| struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev); |
| |
| if (status == SDW_SLAVE_UNATTACHED) |
| rt1320->hw_init = false; |
| |
| /* |
| * Perform initialization only if slave status is present and |
| * hw_init flag is false |
| */ |
| if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED) |
| return 0; |
| |
| /* perform I/O transfers required for Slave initialization */ |
| return rt1320_io_init(&slave->dev, slave); |
| } |
| |
| static int rt1320_pde23_event(struct snd_soc_dapm_widget *w, |
| struct snd_kcontrol *kcontrol, int event) |
| { |
| struct snd_soc_component *component = |
| snd_soc_dapm_to_component(w->dapm); |
| struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); |
| unsigned char ps0 = 0x0, ps3 = 0x3; |
| |
| switch (event) { |
| case SND_SOC_DAPM_POST_PMU: |
| regmap_write(rt1320->regmap, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, |
| RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0); |
| rt1320_pde_transition_delay(rt1320, ps0); |
| break; |
| case SND_SOC_DAPM_PRE_PMD: |
| regmap_write(rt1320->regmap, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, |
| RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3); |
| rt1320_pde_transition_delay(rt1320, ps3); |
| break; |
| default: |
| break; |
| } |
| |
| return 0; |
| } |
| |
| static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
| struct soc_mixer_control *mc = |
| (struct soc_mixer_control *)kcontrol->private_value; |
| struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); |
| unsigned int gain_l_val, gain_r_val; |
| unsigned int lvalue, rvalue; |
| const unsigned int interval_offset = 0xc0; |
| |
| regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue); |
| regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue); |
| |
| /* L Channel */ |
| gain_l_val = ucontrol->value.integer.value[0]; |
| if (gain_l_val > mc->max) |
| gain_l_val = mc->max; |
| gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset); |
| gain_l_val &= 0xffff; |
| |
| /* R Channel */ |
| gain_r_val = ucontrol->value.integer.value[1]; |
| if (gain_r_val > mc->max) |
| gain_r_val = mc->max; |
| gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset); |
| gain_r_val &= 0xffff; |
| |
| if (lvalue == gain_l_val && rvalue == gain_r_val) |
| return 0; |
| |
| /* Lch*/ |
| regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val); |
| /* Rch */ |
| regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val); |
| |
| return 1; |
| } |
| |
| static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol, |
| struct snd_ctl_elem_value *ucontrol) |
| { |
| struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
| struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); |
| struct soc_mixer_control *mc = |
| (struct soc_mixer_control *)kcontrol->private_value; |
| unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0; |
| const unsigned int interval_offset = 0xc0; |
| |
| regmap_read(rt1320->mbq_regmap, mc->reg, &read_l); |
| regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r); |
| |
| ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset); |
| |
| if (read_l != read_r) |
| ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset); |
| else |
| ctl_r = ctl_l; |
| |
| ucontrol->value.integer.value[0] = ctl_l; |
| ucontrol->value.integer.value[1] = ctl_r; |
| return 0; |
| } |
| |
| static const char * const rt1320_rx_data_ch_select[] = { |
| "L,R", |
| "R,L", |
| "L,L", |
| "R,R", |
| "L,L+R", |
| "R,L+R", |
| "L+R,L", |
| "L+R,R", |
| "L+R,L+R", |
| }; |
| |
| static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0, |
| rt1320_rx_data_ch_select); |
| |
| static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0); |
| |
| static const struct snd_kcontrol_new rt1320_snd_controls[] = { |
| SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume", |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), |
| 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv), |
| SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum), |
| }; |
| |
| static const struct snd_kcontrol_new rt1320_spk_l_dac = |
| SOC_DAPM_SINGLE_AUTODISABLE("Switch", |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), |
| 0, 1, 1); |
| static const struct snd_kcontrol_new rt1320_spk_r_dac = |
| SOC_DAPM_SINGLE_AUTODISABLE("Switch", |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), |
| 0, 1, 1); |
| |
| static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = { |
| /* Audio Interface */ |
| SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0), |
| SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), |
| |
| /* Digital Interface */ |
| SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0), |
| SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0, |
| rt1320_pde23_event, |
| SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| |
| /* Output */ |
| SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac), |
| SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac), |
| SND_SOC_DAPM_OUTPUT("SPOL"), |
| SND_SOC_DAPM_OUTPUT("SPOR"), |
| |
| /* Input */ |
| SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0), |
| SND_SOC_DAPM_SIGGEN("AEC Gen"), |
| }; |
| |
| static const struct snd_soc_dapm_route rt1320_dapm_routes[] = { |
| { "FU21", NULL, "DP1RX" }, |
| { "FU21", NULL, "PDE 23" }, |
| { "OT23 L", "Switch", "FU21" }, |
| { "OT23 R", "Switch", "FU21" }, |
| { "SPOL", NULL, "OT23 L" }, |
| { "SPOR", NULL, "OT23 R" }, |
| |
| { "AEC Data", NULL, "AEC Gen" }, |
| { "DP4TX", NULL, "AEC Data" }, |
| }; |
| |
| static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, |
| int direction) |
| { |
| snd_soc_dai_dma_data_set(dai, direction, sdw_stream); |
| return 0; |
| } |
| |
| static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream, |
| struct snd_soc_dai *dai) |
| { |
| snd_soc_dai_set_dma_data(dai, substream, NULL); |
| } |
| |
| static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream, |
| struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
| { |
| struct snd_soc_component *component = dai->component; |
| struct rt1320_sdw_priv *rt1320 = |
| snd_soc_component_get_drvdata(component); |
| struct sdw_stream_config stream_config; |
| struct sdw_port_config port_config; |
| struct sdw_stream_runtime *sdw_stream; |
| int retval; |
| unsigned int sampling_rate; |
| |
| dev_dbg(dai->dev, "%s %s", __func__, dai->name); |
| sdw_stream = snd_soc_dai_get_dma_data(dai, substream); |
| |
| if (!sdw_stream) |
| return -EINVAL; |
| |
| if (!rt1320->sdw_slave) |
| return -EINVAL; |
| |
| /* SoundWire specific configuration */ |
| snd_sdw_params_to_config(substream, params, &stream_config, &port_config); |
| |
| if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| if (dai->id == RT1320_AIF1) |
| port_config.num = 1; |
| else |
| return -EINVAL; |
| } else { |
| if (dai->id == RT1320_AIF1) |
| port_config.num = 4; |
| else |
| return -EINVAL; |
| } |
| |
| retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config, |
| &port_config, 1, sdw_stream); |
| if (retval) { |
| dev_err(dai->dev, "%s: Unable to configure port\n", __func__); |
| return retval; |
| } |
| |
| /* sampling rate configuration */ |
| switch (params_rate(params)) { |
| case 16000: |
| sampling_rate = RT1320_SDCA_RATE_16000HZ; |
| break; |
| case 32000: |
| sampling_rate = RT1320_SDCA_RATE_32000HZ; |
| break; |
| case 44100: |
| sampling_rate = RT1320_SDCA_RATE_44100HZ; |
| break; |
| case 48000: |
| sampling_rate = RT1320_SDCA_RATE_48000HZ; |
| break; |
| case 96000: |
| sampling_rate = RT1320_SDCA_RATE_96000HZ; |
| break; |
| case 192000: |
| sampling_rate = RT1320_SDCA_RATE_192000HZ; |
| break; |
| default: |
| dev_err(component->dev, "%s: Rate %d is not supported\n", |
| __func__, params_rate(params)); |
| return -EINVAL; |
| } |
| |
| /* set sampling frequency */ |
| regmap_write(rt1320->regmap, |
| SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), |
| sampling_rate); |
| |
| return 0; |
| } |
| |
| static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream, |
| struct snd_soc_dai *dai) |
| { |
| struct snd_soc_component *component = dai->component; |
| struct rt1320_sdw_priv *rt1320 = |
| snd_soc_component_get_drvdata(component); |
| struct sdw_stream_runtime *sdw_stream = |
| snd_soc_dai_get_dma_data(dai, substream); |
| |
| if (!rt1320->sdw_slave) |
| return -EINVAL; |
| |
| sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream); |
| return 0; |
| } |
| |
| /* |
| * slave_ops: callbacks for get_clock_stop_mode, clock_stop and |
| * port_prep are not defined for now |
| */ |
| static const struct sdw_slave_ops rt1320_slave_ops = { |
| .read_prop = rt1320_read_prop, |
| .update_status = rt1320_update_status, |
| }; |
| |
| static int rt1320_sdw_component_probe(struct snd_soc_component *component) |
| { |
| int ret; |
| struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component); |
| |
| rt1320->component = component; |
| |
| if (!rt1320->first_hw_init) |
| return 0; |
| |
| ret = pm_runtime_resume(component->dev); |
| dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret); |
| if (ret < 0 && ret != -EACCES) |
| return ret; |
| |
| return 0; |
| } |
| |
| static const struct snd_soc_component_driver soc_component_sdw_rt1320 = { |
| .probe = rt1320_sdw_component_probe, |
| .controls = rt1320_snd_controls, |
| .num_controls = ARRAY_SIZE(rt1320_snd_controls), |
| .dapm_widgets = rt1320_dapm_widgets, |
| .num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets), |
| .dapm_routes = rt1320_dapm_routes, |
| .num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes), |
| .endianness = 1, |
| }; |
| |
| static const struct snd_soc_dai_ops rt1320_aif_dai_ops = { |
| .hw_params = rt1320_sdw_hw_params, |
| .hw_free = rt1320_sdw_pcm_hw_free, |
| .set_stream = rt1320_set_sdw_stream, |
| .shutdown = rt1320_sdw_shutdown, |
| }; |
| |
| #define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
| SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) |
| #define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ |
| SNDRV_PCM_FMTBIT_S32_LE) |
| |
| static struct snd_soc_dai_driver rt1320_sdw_dai[] = { |
| { |
| .name = "rt1320-aif1", |
| .id = RT1320_AIF1, |
| .playback = { |
| .stream_name = "DP1 Playback", |
| .channels_min = 1, |
| .channels_max = 2, |
| .rates = RT1320_STEREO_RATES, |
| .formats = RT1320_FORMATS, |
| }, |
| .capture = { |
| .stream_name = "DP4 Capture", |
| .channels_min = 1, |
| .channels_max = 2, |
| .rates = RT1320_STEREO_RATES, |
| .formats = RT1320_FORMATS, |
| }, |
| .ops = &rt1320_aif_dai_ops, |
| }, |
| }; |
| |
| static int rt1320_sdw_init(struct device *dev, struct regmap *regmap, |
| struct regmap *mbq_regmap, struct sdw_slave *slave) |
| { |
| struct rt1320_sdw_priv *rt1320; |
| int ret; |
| |
| rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL); |
| if (!rt1320) |
| return -ENOMEM; |
| |
| dev_set_drvdata(dev, rt1320); |
| rt1320->sdw_slave = slave; |
| rt1320->mbq_regmap = mbq_regmap; |
| rt1320->regmap = regmap; |
| |
| regcache_cache_only(rt1320->regmap, true); |
| regcache_cache_only(rt1320->mbq_regmap, true); |
| |
| /* |
| * Mark hw_init to false |
| * HW init will be performed when device reports present |
| */ |
| rt1320->hw_init = false; |
| rt1320->first_hw_init = false; |
| rt1320->version_id = -1; |
| |
| ret = devm_snd_soc_register_component(dev, |
| &soc_component_sdw_rt1320, |
| rt1320_sdw_dai, |
| ARRAY_SIZE(rt1320_sdw_dai)); |
| if (ret < 0) |
| return ret; |
| |
| /* set autosuspend parameters */ |
| pm_runtime_set_autosuspend_delay(dev, 3000); |
| pm_runtime_use_autosuspend(dev); |
| |
| /* make sure the device does not suspend immediately */ |
| pm_runtime_mark_last_busy(dev); |
| |
| pm_runtime_enable(dev); |
| |
| /* important note: the device is NOT tagged as 'active' and will remain |
| * 'suspended' until the hardware is enumerated/initialized. This is required |
| * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently |
| * fail with -EACCESS because of race conditions between card creation and enumeration |
| */ |
| |
| dev_dbg(dev, "%s\n", __func__); |
| |
| return ret; |
| } |
| |
| static int rt1320_sdw_probe(struct sdw_slave *slave, |
| const struct sdw_device_id *id) |
| { |
| struct regmap *regmap, *mbq_regmap; |
| |
| /* Regmap Initialization */ |
| mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap); |
| if (IS_ERR(mbq_regmap)) |
| return PTR_ERR(mbq_regmap); |
| |
| regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap); |
| if (IS_ERR(regmap)) |
| return PTR_ERR(regmap); |
| |
| return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave); |
| } |
| |
| static int rt1320_sdw_remove(struct sdw_slave *slave) |
| { |
| pm_runtime_disable(&slave->dev); |
| |
| return 0; |
| } |
| |
| /* |
| * Version A/B will use the class id 0 |
| * The newer version than A/B will use the class id 1, so add it in advance |
| */ |
| static const struct sdw_device_id rt1320_id[] = { |
| SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0), |
| SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0), |
| {}, |
| }; |
| MODULE_DEVICE_TABLE(sdw, rt1320_id); |
| |
| static int __maybe_unused rt1320_dev_suspend(struct device *dev) |
| { |
| struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); |
| |
| if (!rt1320->hw_init) |
| return 0; |
| |
| regcache_cache_only(rt1320->regmap, true); |
| regcache_cache_only(rt1320->mbq_regmap, true); |
| return 0; |
| } |
| |
| #define RT1320_PROBE_TIMEOUT 5000 |
| |
| static int __maybe_unused rt1320_dev_resume(struct device *dev) |
| { |
| struct sdw_slave *slave = dev_to_sdw_dev(dev); |
| struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev); |
| unsigned long time; |
| |
| if (!rt1320->first_hw_init) |
| return 0; |
| |
| if (!slave->unattach_request) |
| goto regmap_sync; |
| |
| time = wait_for_completion_timeout(&slave->initialization_complete, |
| msecs_to_jiffies(RT1320_PROBE_TIMEOUT)); |
| if (!time) { |
| dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__); |
| return -ETIMEDOUT; |
| } |
| |
| regmap_sync: |
| slave->unattach_request = 0; |
| regcache_cache_only(rt1320->regmap, false); |
| regcache_sync(rt1320->regmap); |
| regcache_cache_only(rt1320->mbq_regmap, false); |
| regcache_sync(rt1320->mbq_regmap); |
| return 0; |
| } |
| |
| static const struct dev_pm_ops rt1320_pm = { |
| SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume) |
| SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL) |
| }; |
| |
| static struct sdw_driver rt1320_sdw_driver = { |
| .driver = { |
| .name = "rt1320-sdca", |
| .pm = &rt1320_pm, |
| }, |
| .probe = rt1320_sdw_probe, |
| .remove = rt1320_sdw_remove, |
| .ops = &rt1320_slave_ops, |
| .id_table = rt1320_id, |
| }; |
| module_sdw_driver(rt1320_sdw_driver); |
| |
| MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW"); |
| MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>"); |
| MODULE_LICENSE("GPL"); |
