| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2016 Eckelmann AG. |
| * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| |
| #include "imx6dl.dtsi" |
| |
| / { |
| model = "Eckelmann CI 4X10 Board"; |
| compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; |
| |
| chosen { |
| stdout-path = &uart3; |
| }; |
| |
| memory@10000000 { |
| device_type = "memory"; |
| reg = <0x10000000 0x40000000>; |
| }; |
| |
| rmii_clk: clock-rmii { |
| /* This clock is provided by the phy (KSZ8091RNB) */ |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <50000000>; |
| }; |
| |
| reg_usb_h1_vbus: regulator-usb-h1-vbus { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_h1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| siox { |
| compatible = "eckelmann,siox-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_siox>; |
| din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; |
| dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; |
| dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; |
| dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| &can1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| status = "okay"; |
| }; |
| |
| &can2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| status = "okay"; |
| }; |
| |
| &ecspi2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi2>; |
| cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| flash@0 { |
| compatible = "everspin,mr25h256"; |
| reg = <0>; |
| spi-max-frequency = <15000000>; |
| }; |
| }; |
| |
| &ecspi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi1>; |
| cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| tpm@0 { |
| compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; |
| reg = <0>; |
| spi-max-frequency = <10000000>; |
| }; |
| }; |
| |
| &gpio2 { |
| gpio-line-names = "buzzer", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpio4 { |
| gpio-line-names = "", "", "", "", "", "", "", "in2", |
| "prio2", "prio1", "aux", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpio6 { |
| gpio-line-names = "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "in1", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| temperature-sensor@49 { |
| compatible = "ad,ad7414"; |
| reg = <0x49>; |
| }; |
| |
| rtc@51 { |
| compatible = "nxp,pcf2127"; |
| reg = <0x51>; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| pinctrl_hog: hog { |
| fsl,pins = < |
| MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ |
| MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ |
| MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ |
| MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ |
| MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ |
| MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ |
| MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ |
| MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ |
| |
| >; |
| }; |
| |
| pinctrl_ecspi1: ecspi1grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 |
| MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 |
| MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 |
| MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 |
| >; |
| }; |
| |
| pinctrl_ecspi2: ecspi2grp { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 |
| MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 |
| MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 |
| MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 |
| >; |
| }; |
| |
| pinctrl_enet: enetgrp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 |
| MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 |
| MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 |
| MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 |
| MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 |
| MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 |
| MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 |
| MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 |
| MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 |
| MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 |
| MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 |
| MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| /* without SION i2c doesn't detect bus busy */ |
| MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 |
| MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 |
| >; |
| }; |
| |
| pinctrl_pcie: pciegrp { |
| fsl,pins = < |
| MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 |
| >; |
| }; |
| |
| pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 |
| >; |
| }; |
| |
| pinctrl_siox: sioxgrp { |
| fsl,pins = < |
| MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ |
| MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ |
| MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ |
| MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ |
| >; |
| }; |
| |
| pinctrl_uart1_dte: uart1grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 |
| MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 |
| MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 |
| MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 |
| MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ |
| MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ |
| MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ |
| >; |
| }; |
| |
| pinctrl_uart2_dte: uart2grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 |
| MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 |
| MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 |
| MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 |
| MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ |
| MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ |
| MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ |
| >; |
| }; |
| |
| pinctrl_uart3_dce: uart3grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 |
| MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 |
| >; |
| }; |
| |
| pinctrl_uart4_dce: uart4grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 |
| MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 |
| MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 |
| >; |
| }; |
| |
| pinctrl_uart5_dce: uart5grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 |
| MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 |
| MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ |
| >; |
| }; |
| |
| pinctrl_usbh1: usbh1grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 |
| >; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet>; |
| phy-mode = "rmii"; |
| phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; |
| phy-handle = <&phy>; |
| clocks = <&clks IMX6QDL_CLK_ENET>, |
| <&clks IMX6QDL_CLK_ENET>, |
| <&rmii_clk>, |
| <&clks IMX6QDL_CLK_ENET_REF>; |
| clock-names = "ipg", "ahb", "ptp", "enet_out"; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| phy: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &pcie { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie>; |
| reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1_dte>; |
| uart-has-rtscts; |
| fsl,dte-mode; |
| dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; |
| dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; |
| dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2_dte>; |
| uart-has-rtscts; |
| fsl,dte-mode; |
| dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; |
| dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; |
| dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3_dce>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4_dce>; |
| rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &uart5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart5_dce>; |
| rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| &usbh1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbh1>; |
| vbus-supply = <®_usb_h1_vbus>; |
| status = "okay"; |
| }; |
| |
| &usbotg { |
| dr_mode = "peripheral"; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
