| Device-Tree bindings for Xilinx SPDIF IP |
| The IP supports playback and capture of SPDIF audio |
| - compatible: "xlnx,spdif-2.0" |
| - clock-names: List of input clocks. |
| Required elements: "s_axi_aclk", "aud_clk_i" |
| - clocks: Input clock specifier. Refer to common clock bindings. |
| - reg: Base address and address length of the IP core instance. |
| - interrupts-parent: Phandle for interrupt controller. |
| - interrupts: List of Interrupt numbers. |
| - xlnx,spdif-mode: 0 :- receiver mode |
| - xlnx,aud_clk_i: input audio clock value. |
| spdif_0: spdif@80010000 { |
| clock-names = "aud_clk_i", "s_axi_aclk"; |
| clocks = <&misc_clk_0>, <&clk 71>; |
| compatible = "xlnx,spdif-2.0"; |
| interrupt-names = "spdif_interrupt"; |
| interrupt-parent = <&gic>; |
| reg = <0x0 0x80010000 0x0 0x10000>; |
| xlnx,aud_clk_i = <49152913>; |