| // SPDX-License-Identifier: MIT |
| /* |
| * Copyright © 2014-2019 Intel Corporation |
| * |
| * Authors: |
| * Vinit Azad <vinit.azad@intel.com> |
| * Ben Widawsky <ben@bwidawsk.net> |
| * Dave Gordon <david.s.gordon@intel.com> |
| * Alex Dai <yu.dai@intel.com> |
| */ |
| |
| #include "gt/intel_gt.h" |
| #include "intel_guc_fw.h" |
| #include "i915_drv.h" |
| |
| /** |
| * intel_guc_fw_init_early() - initializes GuC firmware struct |
| * @guc: intel_guc struct |
| * |
| * On platforms with GuC selects firmware for uploading |
| */ |
| void intel_guc_fw_init_early(struct intel_guc *guc) |
| { |
| struct drm_i915_private *i915 = guc_to_gt(guc)->i915; |
| |
| intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915), |
| INTEL_INFO(i915)->platform, INTEL_REVID(i915)); |
| } |
| |
| static void guc_prepare_xfer(struct intel_uncore *uncore) |
| { |
| u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES | |
| GUC_ENABLE_READ_CACHE_LOGIC | |
| GUC_ENABLE_MIA_CACHING | |
| GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | |
| GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | |
| GUC_ENABLE_MIA_CLOCK_GATING; |
| |
| /* Must program this register before loading the ucode with DMA */ |
| intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); |
| |
| if (IS_GEN9_LP(uncore->i915)) |
| intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
| else |
| intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); |
| |
| if (IS_GEN(uncore->i915, 9)) { |
| /* DOP Clock Gating Enable for GuC clocks */ |
| intel_uncore_rmw(uncore, GEN7_MISCCPCTL, |
| 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE); |
| |
| /* allows for 5us (in 10ns units) before GT can go to RC6 */ |
| intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); |
| } |
| } |
| |
| /* Copy RSA signature from the fw image to HW for verification */ |
| static void guc_xfer_rsa(struct intel_uc_fw *guc_fw, |
| struct intel_uncore *uncore) |
| { |
| u32 rsa[UOS_RSA_SCRATCH_COUNT]; |
| size_t copied; |
| int i; |
| |
| copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa)); |
| GEM_BUG_ON(copied < sizeof(rsa)); |
| |
| for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) |
| intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]); |
| } |
| |
| /* |
| * Read the GuC status register (GUC_STATUS) and store it in the |
| * specified location; then return a boolean indicating whether |
| * the value matches either of two values representing completion |
| * of the GuC boot process. |
| * |
| * This is used for polling the GuC status in a wait_for() |
| * loop below. |
| */ |
| static inline bool guc_ready(struct intel_uncore *uncore, u32 *status) |
| { |
| u32 val = intel_uncore_read(uncore, GUC_STATUS); |
| u32 uk_val = val & GS_UKERNEL_MASK; |
| |
| *status = val; |
| return (uk_val == GS_UKERNEL_READY) || |
| ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE)); |
| } |
| |
| static int guc_wait_ucode(struct intel_uncore *uncore) |
| { |
| u32 status; |
| int ret; |
| |
| /* |
| * Wait for the GuC to start up. |
| * NB: Docs recommend not using the interrupt for completion. |
| * Measurements indicate this should take no more than 20ms, so a |
| * timeout here indicates that the GuC has failed and is unusable. |
| * (Higher levels of the driver may decide to reset the GuC and |
| * attempt the ucode load again if this happens.) |
| */ |
| ret = wait_for(guc_ready(uncore, &status), 100); |
| DRM_DEBUG_DRIVER("GuC status %#x\n", status); |
| |
| if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { |
| DRM_ERROR("GuC firmware signature verification failed\n"); |
| ret = -ENOEXEC; |
| } |
| |
| if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) { |
| DRM_ERROR("GuC firmware exception. EIP: %#x\n", |
| intel_uncore_read(uncore, SOFT_SCRATCH(13))); |
| ret = -ENXIO; |
| } |
| |
| return ret; |
| } |
| |
| /** |
| * intel_guc_fw_upload() - load GuC uCode to device |
| * @guc: intel_guc structure |
| * |
| * Called from intel_uc_init_hw() during driver load, resume from sleep and |
| * after a GPU reset. |
| * |
| * The firmware image should have already been fetched into memory, so only |
| * check that fetch succeeded, and then transfer the image to the h/w. |
| * |
| * Return: non-zero code on error |
| */ |
| int intel_guc_fw_upload(struct intel_guc *guc) |
| { |
| struct intel_gt *gt = guc_to_gt(guc); |
| struct intel_uncore *uncore = gt->uncore; |
| int ret; |
| |
| guc_prepare_xfer(uncore); |
| |
| /* |
| * Note that GuC needs the CSS header plus uKernel code to be copied |
| * by the DMA engine in one operation, whereas the RSA signature is |
| * loaded via MMIO. |
| */ |
| guc_xfer_rsa(&guc->fw, uncore); |
| |
| /* |
| * Current uCode expects the code to be loaded at 8k; locations below |
| * this are used for the stack. |
| */ |
| ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); |
| if (ret) |
| goto out; |
| |
| ret = guc_wait_ucode(uncore); |
| if (ret) |
| goto out; |
| |
| intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING); |
| return 0; |
| |
| out: |
| intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL); |
| return ret; |
| } |