| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2022 PHYTEC Messtechnik GmbH |
| * Author: Teresa Remmet <t.remmet@phytec.de> |
| */ |
| |
| #include "imx8mm.dtsi" |
| #include <dt-bindings/net/ti-dp83867.h> |
| |
| / { |
| model = "PHYTEC phyCORE-i.MX8MM"; |
| compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; |
| |
| aliases { |
| rtc0 = &rv3028; |
| rtc1 = &snvs_rtc; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x0 0x40000000 0 0x80000000>; |
| }; |
| |
| reg_vdd_3v3_s: regulator-vdd-3v3-s { |
| compatible = "regulator-fixed"; |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "VDD_3V3_S"; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <®_vdd_arm>; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-25000000 { |
| opp-hz = /bits/ 64 <25000000>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| |
| opp-750000000 { |
| opp-hz = /bits/ 64 <750000000>; |
| }; |
| }; |
| }; |
| |
| /* Ethernet */ |
| &fec1 { |
| fsl,magic-packet; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| enet-phy-lane-no-swap; |
| ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| reg = <0>; |
| reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| reset-assert-us = <1000>; |
| reset-deassert-us = <1000>; |
| }; |
| }; |
| }; |
| |
| /* SPI Flash */ |
| &flexspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexspi0>; |
| status = "okay"; |
| |
| som_flash: flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <80000000>; |
| spi-rx-bus-width = <4>; |
| spi-tx-bus-width = <1>; |
| }; |
| }; |
| |
| &gpio1 { |
| gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT", |
| "", "", "", "RESET_ETHPHY", |
| "", "", "nENABLE_FLATLINK"; |
| }; |
| |
| /* I2C1 */ |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default","gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| pmic@8 { |
| compatible = "nxp,pf8121a"; |
| reg = <0x08>; |
| |
| regulators { |
| reg_nvcc_sd1: ldo1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "NVCC_SD1 (LDO1)"; |
| |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| |
| reg_nvcc_sd2: ldo2 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "NVCC_SD2 (LDO2)"; |
| |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| |
| reg_vcc_enet: ldo3 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <2500000>; |
| regulator-min-microvolt = <1500000>; |
| regulator-name = "VCC_ENET_2V5 (LDO3)"; |
| |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| |
| reg_vdda_1v8: ldo4 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microvolt = <1500000>; |
| regulator-name = "VDDA_1V8 (LDO4)"; |
| |
| regulator-state-mem { |
| regulator-on-in-suspend; |
| regulator-suspend-min-microvolt = <1500000>; |
| regulator-suspend-max-microvolt = <1500000>; |
| }; |
| }; |
| |
| reg_soc_vdda_phy: buck1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <900000>; |
| regulator-min-microvolt = <400000>; |
| regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; |
| |
| regulator-state-mem { |
| regulator-on-in-suspend; |
| regulator-suspend-min-microvolt = <400000>; |
| regulator-suspend-max-microvolt = <400000>; |
| }; |
| }; |
| |
| reg_vdd_gpu_dram: buck2 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microvolt = <1000000>; |
| regulator-name = "VDD_GPU_DRAM (BUCK2)"; |
| |
| regulator-state-mem { |
| regulator-on-in-suspend; |
| regulator-suspend-max-microvolt = <1000000>; |
| regulator-suspend-min-microvolt = <1000000>; |
| }; |
| }; |
| |
| reg_vdd_vpu: buck3 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microvolt = <400000>; |
| regulator-name = "VDD_VPU (BUCK3)"; |
| |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| |
| reg_vdd_mipi: buck4 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1050000>; |
| regulator-min-microvolt = <900000>; |
| regulator-name = "VDD_MIPI_0P9 (BUCK4)"; |
| |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| |
| reg_vdd_arm: buck5 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1050000>; |
| regulator-min-microvolt = <400000>; |
| regulator-name = "VDD_ARM (BUCK5)"; |
| |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| |
| reg_vdd_1v8: buck6 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "VDD_1V8 (BUCK6)"; |
| |
| regulator-state-mem { |
| regulator-on-in-suspend; |
| regulator-suspend-max-microvolt = <1800000>; |
| regulator-suspend-min-microvolt = <1800000>; |
| }; |
| }; |
| |
| reg_nvcc_dram: buck7 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1100000>; |
| regulator-min-microvolt = <1100000>; |
| regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; |
| }; |
| |
| reg_vsnvs: vsnvs { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; |
| }; |
| }; |
| }; |
| |
| sn65dsi83: bridge@2d { |
| compatible = "ti,sn65dsi83"; |
| enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sn65dsi83>; |
| reg = <0x2d>; |
| status = "disabled"; |
| }; |
| |
| eeprom@51 { |
| compatible = "atmel,24c32"; |
| pagesize = <32>; |
| reg = <0x51>; |
| vcc-supply = <®_vdd_3v3_s>; |
| }; |
| |
| rv3028: rtc@52 { |
| compatible = "microcrystal,rv3028"; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-parent = <&gpio1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_rtc>; |
| reg = <0x52>; |
| }; |
| }; |
| |
| /* EMMC */ |
| &usdhc3 { |
| assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| keep-power-in-suspend; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| /* Watchdog */ |
| &wdog1 { |
| fsl,ext-reset-output; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 |
| MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 |
| MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 |
| MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 |
| MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 |
| MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 |
| MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 |
| >; |
| }; |
| |
| pinctrl_flexspi0: flexspi0grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 |
| MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
| MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
| MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
| MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
| MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 |
| MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 |
| >; |
| }; |
| |
| pinctrl_rtc: rtcgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 |
| >; |
| }; |
| |
| pinctrl_sn65dsi83: sn65dsi83grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 |
| >; |
| }; |
| }; |
