| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: LPDDR2 SDRAM AC timing parameters for a given speed-bin |
| |
| maintainers: |
| - Krzysztof Kozlowski <krzk@kernel.org> |
| |
| properties: |
| compatible: |
| const: jedec,lpddr2-timings |
| |
| max-freq: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Maximum DDR clock frequency for the speed-bin, in Hz. |
| |
| min-freq: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Minimum DDR clock frequency for the speed-bin, in Hz. |
| |
| tCKESR: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| CKE minimum pulse width during SELF REFRESH (low pulse width during |
| SELF REFRESH) in pico seconds. |
| |
| tDQSCK-max: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| DQS output data access time from CK_t/CK_c in pico seconds. |
| |
| tDQSCK-max-derated: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| DQS output data access time from CK_t/CK_c, temperature de-rated, in pico |
| seconds. |
| |
| tFAW: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Four-bank activate window in pico seconds. |
| |
| tRAS-max-ns: |
| description: | |
| Row active time in nano seconds. |
| |
| tRAS-min: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Row active time in pico seconds. |
| |
| tRCD: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| RAS-to-CAS delay in pico seconds. |
| |
| tRPab: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Row precharge time (all banks) in pico seconds. |
| |
| tRRD: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Active bank A to active bank B in pico seconds. |
| |
| tRTP: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Internal READ to PRECHARGE command delay in pico seconds. |
| |
| tWR: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| WRITE recovery time in pico seconds. |
| |
| tWTR: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Internal WRITE-to-READ command delay in pico seconds. |
| |
| tXP: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Exit power-down to next valid command delay in pico seconds. |
| |
| tZQCL: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Long calibration time in pico seconds. |
| |
| tZQCS: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Short calibration time in pico seconds. |
| |
| tZQinit: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: | |
| Initialization calibration time in pico seconds. |
| |
| required: |
| - compatible |
| - min-freq |
| - max-freq |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| timings { |
| compatible = "jedec,lpddr2-timings"; |
| min-freq = <10000000>; |
| max-freq = <400000000>; |
| tCKESR = <15000>; |
| tDQSCK-max = <5500>; |
| tFAW = <50000>; |
| tRAS-max-ns = <70000>; |
| tRAS-min = <42000>; |
| tRPab = <21000>; |
| tRCD = <18000>; |
| tRRD = <10000>; |
| tRTP = <7500>; |
| tWR = <15000>; |
| tWTR = <7500>; |
| tXP = <7500>; |
| tZQCL = <360000>; |
| tZQCS = <90000>; |
| tZQinit = <1000000>; |
| }; |