arch/arm/boot/dts/qcom-sdx65.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * SDX65 SoC device tree source
 *
 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 */

#include <dt-bindings/clock/qcom,gcc-sdx65.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
	interrupt-parent = <&intc>;

	memory {
		device_type = "memory";
		reg = <0 0>;
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved_memory: reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		cmd_db: reserved-memory@8fee0000 {
			compatible = "qcom,cmd-db";
			reg = <0x8fee0000 0x20000>;
			no-map;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdx65";
			reg = <0x00100000 0x001f7400>;
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		blsp1_uart3: serial@831000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x00831000 0x200>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sdx65-tlmm";
			reg = <0xf100000 0x300000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 109>;
			interrupt-controller;
			interrupt-parent = <&intc>;
			#interrupt-cells = <2>;
		};

		pdc: interrupt-controller@b210000 {
			compatible = "qcom,sdx65-pdc", "qcom,pdc";
			reg = <0xb210000 0x10000>;
			qcom,pdc-ranges = <0 147 52>, <52 266 32>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		intc: interrupt-controller@17800000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			interrupt-parent = <&intc>;
			#interrupt-cells = <3>;
			reg = <0x17800000 0x1000>,
			      <0x17802000 0x1000>;
		};

		timer@17820000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17820000 0x1000>;
			clock-frequency = <19200000>;

			frame@17821000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 7 0x4>,
					     <GIC_SPI 6 0x4>;
				reg = <0x17821000 0x1000>,
				      <0x17822000 0x1000>;
			};

			frame@17823000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 8 0x4>;
				reg = <0x17823000 0x1000>;
				status = "disabled";
			};

			frame@17824000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 9 0x4>;
				reg = <0x17824000 0x1000>;
				status = "disabled";
			};

			frame@17825000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 10 0x4>;
				reg = <0x17825000 0x1000>;
				status = "disabled";
			};

			frame@17826000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 11 0x4>;
				reg = <0x17826000 0x1000>;
				status = "disabled";
			};

			frame@17827000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 12 0x4>;
				reg = <0x17827000 0x1000>;
				status = "disabled";
			};

			frame@17828000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 13 0x4>;
				reg = <0x17828000 0x1000>;
				status = "disabled";
			};

			frame@17829000 {
				frame-number = <7>;
				interrupts = <GIC_SPI 14 0x4>;
				reg = <0x17829000 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@17830000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x17830000 0x10000>,
			    <0x17840000 0x10000>;
			reg-names = "drv-0", "drv-1";
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				   <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <1>;
			qcom,tcs-config = <ACTIVE_TCS  2>,
				<SLEEP_TCS   2>,
				<WAKE_TCS    2>,
				<CONTROL_TCS 1>;

			rpmhcc: clock-controller@1 {
				compatible = "qcom,sdx65-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			<1 12 0xf08>,
			<1 10 0xf08>,
			<1 11 0xf08>;
		clock-frequency = <19200000>;
	};
};