| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/sound/ti,tlv320adc3xxx.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Texas Instruments TLV320ADC3001/TLV320ADC3101 Stereo ADC |
| |
| maintainers: |
| - Ricard Wanderlof <ricardw@axis.com> |
| |
| description: | |
| Texas Instruments TLV320ADC3001 and TLV320ADC3101 Stereo ADC |
| https://www.ti.com/product/TLV320ADC3001 |
| https://www.ti.com/product/TLV320ADC3101 |
| |
| allOf: |
| - $ref: dai-common.yaml# |
| |
| properties: |
| compatible: |
| enum: |
| - ti,tlv320adc3001 |
| - ti,tlv320adc3101 |
| |
| reg: |
| maxItems: 1 |
| description: I2C address |
| |
| '#sound-dai-cells': |
| const: 0 |
| |
| '#gpio-cells': |
| const: 2 |
| |
| gpio-controller: true |
| |
| reset-gpios: |
| maxItems: 1 |
| description: GPIO pin used for codec reset (RESET pin) |
| |
| clocks: |
| maxItems: 1 |
| description: Master clock (MCLK) |
| |
| ti,dmdin-gpio1: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: |
| - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used |
| - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions |
| - 2 # ADC3XXX_GPIO_GPI - General purpose input |
| - 3 # ADC3XXX_GPIO_GPO - General purpose output |
| - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg |
| - 5 # ADC3XXX_GPIO_INT1 - INT1 output |
| - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK |
| - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK |
| default: 0 |
| description: | |
| Configuration for DMDIN/GPIO1 pin. |
| |
| When ADC3XXX_GPIO_GPO is configured, this causes corresponding the |
| ALSA control "GPIOx Output" to appear, as a switch control. |
| |
| ti,dmclk-gpio2: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: |
| - 0 # ADC3XXX_GPIO_DISABLED - I/O buffers powered down and not used |
| - 1 # ADC3XXX_GPIO_INPUT - Various non-GPIO input functions |
| - 2 # ADC3XXX_GPIO_GPI - General purpose input |
| - 3 # ADC3XXX_GPIO_GPO - General purpose output |
| - 4 # ADC3XXX_GPIO_CLKOUT - Clock source set in CLKOUT_MUX reg |
| - 5 # ADC3XXX_GPIO_INT1 - INT1 output |
| - 6 # ADC3XXX_GPIO_SECONDARY_BCLK - Codec interface secondary BCLK |
| - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK |
| default: 0 |
| description: | |
| Configuration for DMCLK/GPIO2 pin. |
| |
| When ADC3XXX_GPIO_GPO is configured, this causes corresponding the |
| ALSA control "GPIOx Output" to appear, as a switch control. |
| |
| Note that there is currently no support for reading the GPIO pins as |
| inputs. |
| |
| ti,micbias1-vg: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: |
| - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down |
| - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V |
| - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V |
| - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply |
| default: 0 |
| description: | |
| Mic bias voltage output on MICBIAS1 pin |
| |
| ti,micbias2-vg: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: |
| - 0 # ADC3XXX_MICBIAS_OFF - Mic bias is powered down |
| - 1 # ADC3XXX_MICBIAS_2_0V - Mic bias is set to 2.0V |
| - 2 # ADC3XXX_MICBIAS_2_5V - Mic bias is set to 2.5V |
| - 3 # ADC3XXX_MICBIAS_AVDD - Mic bias is same as AVDD supply |
| default: 0 |
| description: | |
| Mic bias voltage output on MICBIAS2 pin |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/sound/tlv320adc3xxx.h> |
| |
| i2c { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| tlv320adc3101: audio-codec@18 { |
| compatible = "ti,tlv320adc3101"; |
| reg = <0x18>; |
| reset-gpios = <&gpio_pc 3 GPIO_ACTIVE_LOW>; |
| clocks = <&audio_mclk>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ti,dmdin-gpio1 = <ADC3XXX_GPIO_GPO>; |
| ti,micbias1-vg = <ADC3XXX_MICBIAS_AVDD>; |
| }; |
| }; |
| |
| audio_mclk: clock { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24576000>; |
| }; |
| ... |