| [ |
| { |
| "EventCode": "0x54", |
| "UMask": "0x1", |
| "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.ABORT_CONFLICT", |
| "PublicDescription": "Number of times a TSX line had a cache conflict.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x54", |
| "UMask": "0x2", |
| "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.ABORT_CAPACITY", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x54", |
| "UMask": "0x4", |
| "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", |
| "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x54", |
| "UMask": "0x8", |
| "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", |
| "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x54", |
| "UMask": "0x10", |
| "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", |
| "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x54", |
| "UMask": "0x20", |
| "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", |
| "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x54", |
| "UMask": "0x40", |
| "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", |
| "PublicDescription": "Number of times we could not allocate Lock Buffer.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x5d", |
| "UMask": "0x1", |
| "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_EXEC.MISC1", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x5d", |
| "UMask": "0x2", |
| "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_EXEC.MISC2", |
| "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x5d", |
| "UMask": "0x4", |
| "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_EXEC.MISC3", |
| "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x5d", |
| "UMask": "0x8", |
| "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_EXEC.MISC4", |
| "PublicDescription": "RTM region detected inside HLE.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x5d", |
| "UMask": "0x10", |
| "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", |
| "Counter": "0,1,2,3", |
| "EventName": "TX_EXEC.MISC5", |
| "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x10", |
| "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x10", |
| "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", |
| "CounterMask": "6", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x10", |
| "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", |
| "CounterMask": "1", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xA3", |
| "UMask": "0x2", |
| "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", |
| "Counter": "0,1,2,3", |
| "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", |
| "CounterMask": "2", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xA3", |
| "UMask": "0x6", |
| "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", |
| "Counter": "0,1,2,3", |
| "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", |
| "CounterMask": "6", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB0", |
| "UMask": "0x10", |
| "BriefDescription": "Demand Data Read requests who miss L3 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", |
| "PublicDescription": "Demand Data Read requests who miss L3 cache.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC3", |
| "UMask": "0x2", |
| "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", |
| "Counter": "0,1,2,3", |
| "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", |
| "Errata": "SKL089", |
| "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x1", |
| "BriefDescription": "Number of times an HLE execution started.", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.START", |
| "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x2", |
| "BriefDescription": "Number of times an HLE execution successfully committed", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.COMMIT", |
| "PublicDescription": "Number of times HLE commit succeeded.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x4", |
| "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.ABORTED", |
| "PublicDescription": "Number of times HLE abort was triggered.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x8", |
| "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.ABORTED_MEM", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x10", |
| "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.ABORTED_TIMER", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x20", |
| "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x40", |
| "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", |
| "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC8", |
| "UMask": "0x80", |
| "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", |
| "Counter": "0,1,2,3", |
| "EventName": "HLE_RETIRED.ABORTED_EVENTS", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x1", |
| "BriefDescription": "Number of times an RTM execution started.", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.START", |
| "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x2", |
| "BriefDescription": "Number of times an RTM execution successfully committed", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.COMMIT", |
| "PublicDescription": "Number of times RTM commit succeeded.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x4", |
| "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.ABORTED", |
| "PublicDescription": "Number of times RTM abort was triggered.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x8", |
| "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.ABORTED_MEM", |
| "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x10", |
| "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.ABORTED_TIMER", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x20", |
| "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", |
| "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x40", |
| "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", |
| "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC9", |
| "UMask": "0x80", |
| "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", |
| "Counter": "0,1,2,3", |
| "EventName": "RTM_RETIRED.ABORTED_EVENTS", |
| "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x200", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "101", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x100", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "503", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x80", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "1009", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x40", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "2003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x20", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "100007", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x10", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "20011", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x8", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "50021", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xCD", |
| "UMask": "0x1", |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", |
| "PEBS": "2", |
| "MSRValue": "0x4", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", |
| "TakenAlone": "1", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0084000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0104000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0204000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0404000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0804000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1004000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F84000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x0090000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x0110000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x0210000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0410000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0810000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x1010000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F90000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00840007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x01040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x02040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x04040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x08040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x10040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F840007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00900007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x01100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x02100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x04100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x08100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x10100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3F900007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE", |
| "Deprecated": "1", |
| "MSRValue": "0x00BC0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", |
| "Deprecated": "1", |
| "MSRValue": "0x013C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS", |
| "Deprecated": "1", |
| "MSRValue": "0x023C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x043C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x083C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", |
| "Deprecated": "1", |
| "MSRValue": "0x103C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP", |
| "Deprecated": "1", |
| "MSRValue": "0x3FBC0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B808000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B800122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x0604000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x063B8007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "Deprecated": "1", |
| "MSRValue": "0x06040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC08000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC00122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM", |
| "Deprecated": "1", |
| "MSRValue": "0x103FC007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L2_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L3_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00400", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=PF_L1D_AND_SW:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC08000", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=OTHER:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00490", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00120", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_PF_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00491", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_DATA_RD:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC00122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_RFO:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "\nThis event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", |
| "Deprecated": "1", |
| "MSRValue": "0x083FC007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE:request=ALL_READS:response=L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0084000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0104000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0204000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0404000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0804000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1004000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F84000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0090000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0110000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0210000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0410000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0810000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1010000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F90000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x00BC000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x013C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x023C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x043C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x083C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x103C000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x3FBC000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0084000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0104000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0204000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0404000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0804000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1004000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F84000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0090000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0110000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0210000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0410000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0810000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1010000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F90000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x00BC000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x013C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x023C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x043C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x083C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x103C000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x3FBC000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0084000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0104000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0204000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0404000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0804000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1004000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F84000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0090000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0110000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0210000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0410000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0810000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1010000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F90000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x00BC000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x013C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x023C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x043C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x083C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x103C000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x3FBC000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0084000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0104000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0204000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0404000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0804000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1004000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F84000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0090000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0110000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0210000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0410000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0810000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1010000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F90000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x00BC000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x013C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x023C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x043C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x083C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x103C000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x3FBC000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0084000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0104000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0204000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0404000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0804000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1004000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F84000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0090000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0110000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0210000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0410000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0810000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1010000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F90000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x00BC000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x013C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x023C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x043C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x083C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x103C000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x3FBC000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0084000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0104000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0204000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0404000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0804000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1004000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F84000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0090000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0110000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0210000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0410000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0810000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1010000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F90000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x00BC000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x013C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x023C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x043C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x083C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x103C000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x3FBC000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0084000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0104000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0204000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0404000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0804000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1004000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F84000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0090000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0110000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0210000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0410000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0810000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1010000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F90000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x00BC000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x013C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x023C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x043C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x083C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x103C000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x3FBC000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0084000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0104000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0204000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0404000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0804000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1004000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F84000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0090000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0110000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0210000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0410000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0810000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1010000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F90000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x00BC000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x013C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x023C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x043C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x083C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x103C000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x3FBC000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0084008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0104008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0204008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0404008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0804008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1004008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F84008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0090008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0110008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0210008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0410008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0810008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1010008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F90008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x00BC008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x013C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x023C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x043C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x083C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x103C008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x3FBC008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0084000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0104000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0204000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0404000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0804000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1004000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F84000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0090000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0110000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0210000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0410000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0810000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1010000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F90000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00BC000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x013C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x023C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x043C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x083C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x103C000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3FBC000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0084000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0104000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0204000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0404000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0804000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1004000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F84000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0090000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0110000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0210000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0410000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0810000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1010000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F90000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00BC000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x013C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x023C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x043C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x083C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x103C000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3FBC000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0084000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0104000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0204000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0404000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0804000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1004000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F84000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0090000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0110000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0210000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0410000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0810000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1010000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F90000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00BC000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x013C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x023C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x043C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x083C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x103C000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3FBC000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0084000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0104000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0204000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0404000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0804000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1004000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F84000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0090000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0110000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0210000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0410000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0810000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1010000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F90000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00BC000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x013C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x023C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x043C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x083C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x103C000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3FBC000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00840007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F840007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00900007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10100007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F900007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00BC0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x013C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x023C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x043C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x083C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x103C0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3FBC0007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x063B800001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0604000001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x063B800002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0604000002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x063B800004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0604000004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x063B800010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0604000010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x063B800020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0604000020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x063B800080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0604000080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x063B800100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0604000100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x063B800400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0604000400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x063B808000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0604008000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x063B800490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0604000490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x063B800120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0604000120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x063B800491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0604000491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x063B800122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0604000122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x063B8007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x06040007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x103FC00001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x103FC00002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x103FC00004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x103FC00010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x103FC00020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x103FC00080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x103FC00100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x103FC00400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x103FC08000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x103FC00490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x103FC00120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x103FC00491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x103FC00122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x103FC007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x083FC00001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x083FC00002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x083FC00004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x083FC00010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x083FC00020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x083FC00080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x083FC00100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x083FC00400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x083FC08000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x083FC00490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x083FC00120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x083FC00491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x083FC00122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x083FC007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| } |
| ] |
