| [ |
| { |
| "EventCode": "0x09", |
| "UMask": "0x1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x28", |
| "UMask": "0x7", |
| "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", |
| "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x28", |
| "UMask": "0x18", |
| "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", |
| "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x28", |
| "UMask": "0x20", |
| "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", |
| "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x28", |
| "UMask": "0x40", |
| "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_POWER.THROTTLE", |
| "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x32", |
| "UMask": "0x1", |
| "BriefDescription": "Number of PREFETCHNTA instructions executed.", |
| "Counter": "0,1,2,3", |
| "EventName": "SW_PREFETCH_ACCESS.NTA", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x32", |
| "UMask": "0x2", |
| "BriefDescription": "Number of PREFETCHT0 instructions executed.", |
| "Counter": "0,1,2,3", |
| "EventName": "SW_PREFETCH_ACCESS.T0", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x32", |
| "UMask": "0x4", |
| "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", |
| "Counter": "0,1,2,3", |
| "EventName": "SW_PREFETCH_ACCESS.T1_T2", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x32", |
| "UMask": "0x8", |
| "BriefDescription": "Number of PREFETCHW instructions executed.", |
| "Counter": "0,1,2,3", |
| "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xCB", |
| "UMask": "0x1", |
| "BriefDescription": "Number of hardware interrupts received by the processor.", |
| "Counter": "0,1,2,3", |
| "EventName": "HW_INTERRUPTS.RECEIVED", |
| "PublicDescription": "Counts the number of hardware interruptions received by the processor.", |
| "SampleAfterValue": "203", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x1", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x2", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x4", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x8", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x10", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x20", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xEF", |
| "UMask": "0x40", |
| "Counter": "0,1,2,3", |
| "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xFE", |
| "UMask": "0x2", |
| "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", |
| "Counter": "0,1,2,3", |
| "EventName": "IDI_MISC.WB_UPGRADE", |
| "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xFE", |
| "UMask": "0x4", |
| "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", |
| "Counter": "0,1,2,3", |
| "EventName": "IDI_MISC.WB_DOWNGRADE", |
| "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0080020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0100020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0200020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0400020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0800020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1000020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F80020001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0080040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0100040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0200040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0400040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0800040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1000040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F80040001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0080080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0100080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0200080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0400080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0800080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1000080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F80080001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0080100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0100100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0200100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0400100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0800100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1000100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F80100001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0080200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0100200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x0200200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0400200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0800200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x1000200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F80200001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x00803C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x01003C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x02003C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x04003C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x08003C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x10003C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD TBD", |
| "MSRValue": "0x3F803C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0080020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0100020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0200020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0400020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0800020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1000020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F80020002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0080040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0100040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0200040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0400040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0800040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1000040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F80040002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0080080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0100080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0200080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0400080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0800080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1000080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F80080002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0080100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0100100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0200100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0400100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0800100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1000100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F80100002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0080200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0100200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x0200200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0400200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0800200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x1000200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F80200002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x00803C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x01003C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x02003C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x04003C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x08003C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x10003C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD TBD", |
| "MSRValue": "0x3F803C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0080020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0100020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0200020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0400020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0800020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1000020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F80020004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0080040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0100040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0200040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0400040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0800040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1000040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F80040004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0080080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0100080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0200080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0400080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0800080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1000080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F80080004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0080100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0100100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0200100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0400100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0800100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1000100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F80100004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0080200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0100200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x0200200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0400200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0800200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x1000200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F80200004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x00803C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x01003C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x02003C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x04003C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x08003C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x10003C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD TBD", |
| "MSRValue": "0x3F803C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0080020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0100020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0200020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0400020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0800020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1000020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F80020010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0080040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0100040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0200040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0400040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0800040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1000040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F80040010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0080080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0100080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0200080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0400080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0800080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1000080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F80080010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0080100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0100100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0200100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0400100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0800100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1000100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F80100010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0080200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0100200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x0200200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0400200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0800200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x1000200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F80200010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x00803C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x01003C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x02003C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x04003C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x08003C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x10003C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD TBD", |
| "MSRValue": "0x3F803C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0080020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0100020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0200020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0400020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0800020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1000020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F80020020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0080040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0100040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0200040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0400040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0800040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1000040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F80040020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0080080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0100080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0200080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0400080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0800080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1000080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F80080020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0080100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0100100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0200100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0400100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0800100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1000100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F80100020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0080200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0100200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x0200200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0400200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0800200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x1000200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F80200020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x00803C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x01003C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x02003C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x04003C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x08003C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x10003C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD TBD", |
| "MSRValue": "0x3F803C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0080020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0100020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0200020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0400020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0800020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1000020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F80020080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0080040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0100040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0200040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0400040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0800040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1000040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F80040080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0080080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0100080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0200080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0400080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0800080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1000080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F80080080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0080100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0100100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0200100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0400100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0800100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1000100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F80100080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0080200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0100200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x0200200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0400200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0800200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x1000200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F80200080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x00803C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x01003C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x02003C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x04003C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x08003C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x10003C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD TBD", |
| "MSRValue": "0x3F803C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0080020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0100020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0200020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0400020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0800020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1000020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F80020100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0080040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0100040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0200040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0400040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0800040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1000040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F80040100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0080080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0100080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0200080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0400080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0800080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1000080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F80080100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0080100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0100100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0200100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0400100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0800100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1000100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F80100100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0080200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0100200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x0200200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0400200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0800200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x1000200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F80200100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x00803C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x01003C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x02003C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x04003C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x08003C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x10003C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD TBD", |
| "MSRValue": "0x3F803C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0080020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0100020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0200020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0400020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0800020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1000020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F80020400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0080040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0100040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0200040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0400040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0800040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1000040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F80040400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0080080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0100080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0200080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0400080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0800080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1000080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F80080400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0080100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0100100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0200100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0400100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0800100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1000100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F80100400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0080200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0100200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x0200200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0400200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0800200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x1000200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F80200400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x00803C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x01003C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x02003C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x04003C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x08003C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x10003C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD TBD", |
| "MSRValue": "0x3F803C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0080028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0100028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0200028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0400028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0800028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1000028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F80028000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0080048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0100048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0200048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0400048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0800048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1000048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F80048000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0080088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0100088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0200088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0400088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0800088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1000088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F80088000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0080108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0100108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0200108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0400108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0800108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1000108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F80108000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0080208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0100208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x0200208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0400208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0800208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x1000208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F80208000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x00803C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x01003C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x02003C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x04003C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x08003C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x10003C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD TBD", |
| "MSRValue": "0x3F803C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80020490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80040490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80080490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80100490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80200490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00803C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x01003C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x02003C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x04003C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x08003C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x10003C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3F803C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80020120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80040120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80080120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80100120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80200120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00803C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x01003C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x02003C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x04003C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x08003C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x10003C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3F803C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80020491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80040491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80080491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80100491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80200491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00803C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x01003C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x02003C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x04003C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x08003C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x10003C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3F803C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80020122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80040122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80080122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80100122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0080200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x0200200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0400200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0800200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x1000200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80200122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00803C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x01003C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x02003C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x04003C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x08003C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x10003C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3F803C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00800207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01000207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02000207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04000207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08000207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10000207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F800207F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00800407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01000407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02000407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04000407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08000407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10000407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F800407F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00800807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01000807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02000807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04000807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08000807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10000807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F800807F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00801007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01001007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02001007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04001007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08001007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10001007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F801007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x00802007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01002007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x02002007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x04002007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x08002007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x10002007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F802007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00803C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x01003C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x02003C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x04003C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x08003C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x10003C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD TBD", |
| "MSRValue": "0x3F803C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads have any response type.", |
| "MSRValue": "0x0000010001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads", |
| "MSRValue": "0x08007C0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", |
| "MSRValue": "0x0000010002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs)", |
| "MSRValue": "0x08007C0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads have any response type.", |
| "MSRValue": "0x0000010004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads", |
| "MSRValue": "0x08007C0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", |
| "MSRValue": "0x0000010010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads", |
| "MSRValue": "0x08007C0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", |
| "MSRValue": "0x0000010020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", |
| "MSRValue": "0x08007C0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", |
| "MSRValue": "0x0000010080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", |
| "MSRValue": "0x08007C0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", |
| "MSRValue": "0x0000010100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", |
| "MSRValue": "0x08007C0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", |
| "MSRValue": "0x0000010400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", |
| "MSRValue": "0x08007C0400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests have any response type.", |
| "MSRValue": "0x0000018000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests", |
| "MSRValue": "0x08007C8000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD have any response type.", |
| "MSRValue": "0x0000010490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x08007C0490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD have any response type.", |
| "MSRValue": "0x0000010120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x08007C0120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD have any response type.", |
| "MSRValue": "0x0000010491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x08007C0491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD have any response type.", |
| "MSRValue": "0x0000010122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x08007C0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD have any response type.", |
| "MSRValue": "0x00000107F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", |
| "MSRValue": "0x01003C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD", |
| "MSRValue": "0x08007C07F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0100400001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x0080400001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0100400002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x0080400002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0100400004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x0080400004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0100400010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x0080400010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0100400020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x0080400020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0100400080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x0080400080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0100400100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x0080400100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0100400400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x0080400400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0100408000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x0080408000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100400490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0080400490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100400120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0080400120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100400491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0080400491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0100400122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x0080400122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x01004007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x00804007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads TBD", |
| "MSRValue": "0x3F80400001", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) TBD", |
| "MSRValue": "0x3F80400002", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads TBD", |
| "MSRValue": "0x3F80400004", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads TBD", |
| "MSRValue": "0x3F80400010", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs TBD", |
| "MSRValue": "0x3F80400020", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads TBD", |
| "MSRValue": "0x3F80400080", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs TBD", |
| "MSRValue": "0x3F80400100", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests TBD", |
| "MSRValue": "0x3F80400400", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts any other requests TBD", |
| "MSRValue": "0x3F80408000", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80400490", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80400120", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80400491", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F80400122", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "TBD TBD", |
| "MSRValue": "0x3F804007F7", |
| "Counter": "0,1,2,3", |
| "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| } |
| ] |