| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for Marvell Armada 370 family SoC |
| * |
| * Copyright (C) 2012 Marvell |
| * |
| * Lior Amsalem <alior@marvell.com> |
| * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| * |
| * Contains definitions specific to the Armada 370 SoC that are not |
| * common to all Armada SoCs. |
| */ |
| |
| #include "armada-370-xp.dtsi" |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| model = "Marvell Armada 370 family SoC"; |
| compatible = "marvell,armada370", "marvell,armada-370-xp"; |
| |
| aliases { |
| gpio0 = &gpio0; |
| gpio1 = &gpio1; |
| gpio2 = &gpio2; |
| }; |
| |
| soc { |
| compatible = "marvell,armada370-mbus", "simple-bus"; |
| |
| bootrom { |
| compatible = "marvell,bootrom"; |
| reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; |
| }; |
| |
| pciec: pcie@82000000 { |
| compatible = "marvell,armada-370-pcie"; |
| status = "disabled"; |
| device_type = "pci"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| msi-parent = <&mpic>; |
| bus-range = <0x00 0xff>; |
| |
| ranges = |
| <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
| 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 |
| 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
| 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ |
| 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ |
| 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; |
| |
| pcie0: pcie@1,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; |
| reg = <0x0800 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
| 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
| bus-range = <0x00 0xff>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &mpic 58>; |
| marvell,pcie-port = <0>; |
| marvell,pcie-lane = <0>; |
| clocks = <&gateclk 5>; |
| status = "disabled"; |
| }; |
| |
| pcie2: pcie@2,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; |
| reg = <0x1000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 |
| 0x81000000 0 0 0x81000000 0x2 0 1 0>; |
| bus-range = <0x00 0xff>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &mpic 62>; |
| marvell,pcie-port = <1>; |
| marvell,pcie-lane = <0>; |
| clocks = <&gateclk 9>; |
| status = "disabled"; |
| }; |
| }; |
| |
| internal-regs { |
| L2: l2-cache@8000 { |
| compatible = "marvell,aurora-outer-cache"; |
| reg = <0x08000 0x1000>; |
| cache-id-part = <0x100>; |
| cache-level = <2>; |
| cache-unified; |
| wt-override; |
| }; |
| |
| gpio0: gpio@18100 { |
| compatible = "marvell,armada-370-gpio", |
| "marvell,orion-gpio"; |
| reg = <0x18100 0x40>, <0x181c0 0x08>; |
| reg-names = "gpio", "pwm"; |
| ngpios = <32>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| #pwm-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <82>, <83>, <84>, <85>; |
| clocks = <&coreclk 0>; |
| }; |
| |
| gpio1: gpio@18140 { |
| compatible = "marvell,armada-370-gpio", |
| "marvell,orion-gpio"; |
| reg = <0x18140 0x40>, <0x181c8 0x08>; |
| reg-names = "gpio", "pwm"; |
| ngpios = <32>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| #pwm-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <87>, <88>, <89>, <90>; |
| clocks = <&coreclk 0>; |
| }; |
| |
| gpio2: gpio@18180 { |
| compatible = "marvell,armada-370-gpio", |
| "marvell,orion-gpio"; |
| reg = <0x18180 0x40>; |
| ngpios = <2>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <91>; |
| }; |
| |
| |
| systemc: system-controller@18200 { |
| compatible = "marvell,armada-370-xp-system-controller"; |
| reg = <0x18200 0x100>; |
| }; |
| |
| gateclk: clock-gating-control@18220 { |
| compatible = "marvell,armada-370-gating-clock"; |
| reg = <0x18220 0x4>; |
| clocks = <&coreclk 0>; |
| #clock-cells = <1>; |
| }; |
| |
| coreclk: mvebu-sar@18230 { |
| compatible = "marvell,armada-370-core-clock"; |
| reg = <0x18230 0x08>; |
| #clock-cells = <1>; |
| }; |
| |
| thermal: thermal@18300 { |
| compatible = "marvell,armada370-thermal"; |
| reg = <0x18300 0x4 |
| 0x18304 0x4>; |
| status = "okay"; |
| }; |
| |
| sscg: sscg@18330 { |
| reg = <0x18330 0x4>; |
| }; |
| |
| cpuconf: cpu-config@21000 { |
| compatible = "marvell,armada-370-cpu-config"; |
| reg = <0x21000 0x8>; |
| }; |
| |
| audio_controller: audio-controller@30000 { |
| #sound-dai-cells = <1>; |
| compatible = "marvell,armada370-audio"; |
| reg = <0x30000 0x4000>; |
| interrupts = <93>; |
| clocks = <&gateclk 0>; |
| clock-names = "internal"; |
| status = "disabled"; |
| }; |
| |
| xor0: xor@60800 { |
| compatible = "marvell,orion-xor"; |
| reg = <0x60800 0x100 |
| 0x60A00 0x100>; |
| status = "okay"; |
| |
| xor00 { |
| interrupts = <51>; |
| dmacap,memcpy; |
| dmacap,xor; |
| }; |
| xor01 { |
| interrupts = <52>; |
| dmacap,memcpy; |
| dmacap,xor; |
| dmacap,memset; |
| }; |
| }; |
| |
| xor1: xor@60900 { |
| compatible = "marvell,orion-xor"; |
| reg = <0x60900 0x100 |
| 0x60b00 0x100>; |
| status = "okay"; |
| |
| xor10 { |
| interrupts = <94>; |
| dmacap,memcpy; |
| dmacap,xor; |
| }; |
| xor11 { |
| interrupts = <95>; |
| dmacap,memcpy; |
| dmacap,xor; |
| dmacap,memset; |
| }; |
| }; |
| |
| cesa: crypto@90000 { |
| compatible = "marvell,armada-370-crypto"; |
| reg = <0x90000 0x10000>; |
| reg-names = "regs"; |
| interrupts = <48>; |
| clocks = <&gateclk 23>; |
| clock-names = "cesa0"; |
| marvell,crypto-srams = <&crypto_sram>; |
| marvell,crypto-sram-size = <0x7e0>; |
| }; |
| }; |
| |
| crypto_sram: sa-sram { |
| compatible = "mmio-sram"; |
| reg = <MBUS_ID(0x09, 0x01) 0 0x800>; |
| reg-names = "sram"; |
| clocks = <&gateclk 23>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; |
| |
| /* |
| * The Armada 370 has an erratum preventing the use of |
| * the standard workflow for CPU idle support (relying |
| * on the BootROM code to enter/exit idle state). |
| * Reserve some amount of the crypto SRAM to put the |
| * cpuidle workaround. |
| */ |
| idle-sram@0 { |
| reg = <0x0 0x20>; |
| }; |
| }; |
| }; |
| }; |
| |
| /* |
| * Default UART pinctrl setting without RTS/CTS, can be overwritten on |
| * board level if a different configuration is used. |
| */ |
| |
| &uart0 { |
| pinctrl-0 = <&uart0_pins>; |
| pinctrl-names = "default"; |
| }; |
| |
| &uart1 { |
| pinctrl-0 = <&uart1_pins>; |
| pinctrl-names = "default"; |
| }; |
| |
| &i2c0 { |
| reg = <0x11000 0x20>; |
| }; |
| |
| &i2c1 { |
| reg = <0x11100 0x20>; |
| }; |
| |
| &mpic { |
| reg = <0x20a00 0x1d0>, <0x21870 0x58>; |
| }; |
| |
| &timer { |
| compatible = "marvell,armada-370-timer"; |
| clocks = <&coreclk 2>; |
| }; |
| |
| &watchdog { |
| compatible = "marvell,armada-370-wdt"; |
| clocks = <&coreclk 2>; |
| }; |
| |
| &usb0 { |
| clocks = <&coreclk 0>; |
| }; |
| |
| &usb1 { |
| clocks = <&coreclk 0>; |
| }; |
| |
| ð0 { |
| compatible = "marvell,armada-370-neta"; |
| }; |
| |
| ð1 { |
| compatible = "marvell,armada-370-neta"; |
| }; |
| |
| &pinctrl { |
| compatible = "marvell,mv88f6710-pinctrl"; |
| |
| spi0_pins1: spi0-pins1 { |
| marvell,pins = "mpp33", "mpp34", |
| "mpp35", "mpp36"; |
| marvell,function = "spi0"; |
| }; |
| |
| spi0_pins2: spi0_pins2 { |
| marvell,pins = "mpp32", "mpp63", |
| "mpp64", "mpp65"; |
| marvell,function = "spi0"; |
| }; |
| |
| spi1_pins: spi1-pins { |
| marvell,pins = "mpp49", "mpp50", |
| "mpp51", "mpp52"; |
| marvell,function = "spi1"; |
| }; |
| |
| uart0_pins: uart0-pins { |
| marvell,pins = "mpp0", "mpp1"; |
| marvell,function = "uart0"; |
| }; |
| |
| uart1_pins: uart1-pins { |
| marvell,pins = "mpp41", "mpp42"; |
| marvell,function = "uart1"; |
| }; |
| |
| sdio_pins1: sdio-pins1 { |
| marvell,pins = "mpp9", "mpp11", "mpp12", |
| "mpp13", "mpp14", "mpp15"; |
| marvell,function = "sd0"; |
| }; |
| |
| sdio_pins2: sdio-pins2 { |
| marvell,pins = "mpp47", "mpp48", "mpp49", |
| "mpp50", "mpp51", "mpp52"; |
| marvell,function = "sd0"; |
| }; |
| |
| sdio_pins3: sdio-pins3 { |
| marvell,pins = "mpp48", "mpp49", "mpp50", |
| "mpp51", "mpp52", "mpp53"; |
| marvell,function = "sd0"; |
| }; |
| |
| i2c0_pins: i2c0-pins { |
| marvell,pins = "mpp2", "mpp3"; |
| marvell,function = "i2c0"; |
| }; |
| |
| i2s_pins1: i2s-pins1 { |
| marvell,pins = "mpp5", "mpp6", "mpp7", |
| "mpp8", "mpp9", "mpp10", |
| "mpp12", "mpp13"; |
| marvell,function = "audio"; |
| }; |
| |
| i2s_pins2: i2s-pins2 { |
| marvell,pins = "mpp49", "mpp47", "mpp50", |
| "mpp59", "mpp57", "mpp61", |
| "mpp62", "mpp60", "mpp58"; |
| marvell,function = "audio"; |
| }; |
| |
| mdio_pins: mdio-pins { |
| marvell,pins = "mpp17", "mpp18"; |
| marvell,function = "ge"; |
| }; |
| |
| ge0_rgmii_pins: ge0-rgmii-pins { |
| marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", |
| "mpp9", "mpp10", "mpp11", "mpp12", |
| "mpp13", "mpp14", "mpp15", "mpp16"; |
| marvell,function = "ge0"; |
| }; |
| |
| ge1_rgmii_pins: ge1-rgmii-pins { |
| marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", |
| "mpp23", "mpp24", "mpp25", "mpp26", |
| "mpp27", "mpp28", "mpp29", "mpp30"; |
| marvell,function = "ge1"; |
| }; |
| }; |
| |
| /* |
| * Default SPI pinctrl setting, can be overwritten on |
| * board level if a different configuration is used. |
| */ |
| &spi0 { |
| compatible = "marvell,armada-370-spi", "marvell,orion-spi"; |
| pinctrl-0 = <&spi0_pins1>; |
| pinctrl-names = "default"; |
| }; |
| |
| &spi1 { |
| compatible = "marvell,armada-370-spi", "marvell,orion-spi"; |
| pinctrl-0 = <&spi1_pins>; |
| pinctrl-names = "default"; |
| }; |
