| // SPDX-License-Identifier: GPL-2.0 or MIT |
| // |
| // Device Tree Source for i.MX6DL based congatec QMX6 |
| // System on Module |
| // |
| // Copyright 2018-2021 General Electric Company |
| // Copyright 2018-2021 Collabora |
| // Copyright 2016 congatec AG |
| |
| #include "imx6dl.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/sound/fsl-imx-audmux.h> |
| |
| / { |
| memory@10000000 { |
| reg = <0x10000000 0x40000000>; |
| }; |
| |
| reg_3p3v: 3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "3P3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| i2cmux { |
| compatible = "i2c-mux-gpio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; |
| i2c-parent = <&i2c2>; |
| |
| i2c5: i2c@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| i2c6: i2c@1 { |
| reg = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| }; |
| |
| &audmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_audmux>; |
| |
| audmux_ssi1 { |
| fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; |
| fsl,port-config = < |
| (IMX_AUDMUX_V2_PTCR_TFSDIR | |
| IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) | |
| IMX_AUDMUX_V2_PTCR_TCLKDIR | |
| IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) | |
| IMX_AUDMUX_V2_PTCR_SYN) |
| IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6) |
| >; |
| }; |
| |
| audmux_aud6 { |
| fsl,audmux-port = <MX51_AUDMUX_PORT6>; |
| fsl,port-config = < |
| IMX_AUDMUX_V2_PTCR_SYN |
| IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) |
| >; |
| }; |
| }; |
| |
| &clks { |
| clocks = <&rtc_sqw>; |
| clock-names = "ckil"; |
| assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| <&clks IMX6QDL_CLK_LDB_DI1_SEL>; |
| assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, |
| <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; |
| }; |
| |
| &ecspi1 { |
| cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi1>; |
| status = "okay"; |
| |
| flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "sst,sst25vf032b", "jedec,spi-nor"; |
| spi-max-frequency = <20000000>; |
| reg = <0>; |
| |
| partition@0 { |
| label = "bootloader"; |
| reg = <0x0000000 0x100000>; |
| }; |
| |
| partition@100000 { |
| label = "user"; |
| reg = <0x0100000 0x2fc000>; |
| }; |
| |
| partition@3fc000 { |
| label = "reserved"; |
| reg = <0x03fc000 0x4000>; |
| read-only; |
| }; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>; |
| phy-mode = "rgmii-id"; |
| phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; |
| fsl,magic-packet; |
| phy-handle = <&phy0>; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| phy0: ethernet-phy@6 { |
| reg = <6>; |
| qca,clk-out-frequency = <125000000>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| pinctrl-1 = <&pinctrl_i2c3_gpio>; |
| scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| rtc: m41t62@68 { |
| compatible = "st,m41t62"; |
| reg = <0x68>; |
| |
| rtc_sqw: clock { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| }; |
| }; |
| |
| &i2c6 { |
| pmic@8 { |
| compatible = "fsl,pfuze100"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1ab { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw1c_reg: sw1c { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3a { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3b_reg: sw3b { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw4_reg: sw4 { |
| regulator-min-microvolt = <675000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* |
| * keep VGEN3, VGEN4 and VGEN5 enabled in order to |
| * maintain backward compatibility with hw-rev. A.0 |
| */ |
| vgen3_reg: vgen3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: vgen4 { |
| regulator-min-microvolt = <2500000>; |
| regulator-max-microvolt = <2500000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vgen5 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| /* supply voltage for eMMC */ |
| vgen6_reg: vgen6 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &pcie { |
| reset-gpio = <&gpio1 20 0>; |
| }; |
| |
| &pwm4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm4>; |
| }; |
| |
| ®_arm { |
| vin-supply = <&sw1a_reg>; |
| }; |
| |
| ®_pu { |
| vin-supply = <&sw1c_reg>; |
| }; |
| |
| ®_soc { |
| vin-supply = <&sw1c_reg>; |
| }; |
| |
| &snvs_poweroff { |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| status = "okay"; |
| }; |
| |
| &usbh1 { |
| /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */ |
| vbus-supply = <®_5v>; |
| status = "okay"; |
| }; |
| |
| &usbotg { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg>; |
| }; |
| |
| &usdhc2 { |
| /* MicroSD card slot */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; |
| no-1-8-v; |
| keep-power-in-suspend; |
| wakeup-source; |
| vmmc-supply = <®_3p3v>; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| /* eMMC module */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| non-removable; |
| bus-width = <8>; |
| no-1-8-v; |
| keep-power-in-suspend; |
| wakeup-source; |
| vmmc-supply = <®_3p3v>; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| qmx6mux: imx6qdl-qmx6 { |
| pinctrl_audmux: audmuxgrp { |
| fsl,pins = < |
| MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */ |
| MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */ |
| MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */ |
| MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */ |
| >; |
| }; |
| |
| /* PHY is on System on Module, Q7[3-15] have Ethernet lines */ |
| pinctrl_enet: enet { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 |
| MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 |
| MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 |
| MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 |
| MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 |
| MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 |
| MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 |
| MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 |
| MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 |
| MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 |
| MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 |
| MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 |
| MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */ |
| MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */ |
| MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */ |
| MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */ |
| MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */ |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */ |
| MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */ |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1-gpio { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */ |
| MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */ |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */ |
| MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */ |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2-gpio { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */ |
| MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */ |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */ |
| MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */ |
| >; |
| }; |
| |
| pinctrl_i2c3_gpio: i2c3-gpio { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */ |
| MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */ |
| >; |
| }; |
| |
| pinctrl_phy_reset: phy-reset { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */ |
| >; |
| }; |
| |
| pinctrl_pwm4: pwm4 { |
| fsl,pins = < |
| MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */ |
| >; |
| }; |
| |
| pinctrl_q7_backlight_enable: q7-backlight-enable { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio0: q7-gpio0 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio1: q7-gpio1 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio2: q7-gpio2 { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio3: q7-gpio3 { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio4: q7-gpio4 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio5: q7-gpio5 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio6: q7-gpio6 { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */ |
| >; |
| }; |
| |
| pinctrl_q7_gpio7: q7-gpio7 { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */ |
| >; |
| }; |
| |
| pinctrl_q7_hda_reset: q7-hda-reset { |
| fsl,pins = < |
| MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */ |
| >; |
| }; |
| |
| pinctrl_q7_lcd_power: lcd-power { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */ |
| >; |
| }; |
| |
| pinctrl_q7_sdio_power: q7-sdio-power { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */ |
| >; |
| }; |
| |
| pinctrl_q7_sleep_button: q7-sleep-button { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */ |
| >; |
| }; |
| |
| pinctrl_q7_spi_cs1: spi-cs1 { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */ |
| >; |
| }; |
| |
| /* SPI1 bus does not leave System on Module */ |
| pinctrl_spi1: spi1 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
| MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 |
| >; |
| }; |
| |
| /* Debug connector on Q7 module */ |
| pinctrl_uart2: uart2 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3 { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */ |
| MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */ |
| >; |
| }; |
| |
| pinctrl_usbotg: usbotg { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */ |
| >; |
| }; |
| |
| /* µSD card slot on Q7 module */ |
| pinctrl_usdhc2: usdhc2 { |
| fsl,pins = < |
| MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */ |
| >; |
| }; |
| |
| /* eMMC module on Q7 module */ |
| pinctrl_usdhc3: usdhc3 { |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc4: usdhc4 { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */ |
| MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */ |
| MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */ |
| MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */ |
| MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */ |
| MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */ |
| >; |
| }; |
| |
| pinctrl_wdog: wdog { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */ |
| >; |
| }; |
| }; |
| }; |
