arch/arm/boot/dts/s3c2416.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C2416 SoC device tree source
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 */

#include <dt-bindings/clock/s3c2443.h>
#include "s3c24xx.dtsi"
#include "s3c2416-pinctrl.dtsi"

/ {
	model = "Samsung S3C2416 SoC";
	compatible = "samsung,s3c2416";

	aliases {
		serial3 = &uart_3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			reg = <0x0>;
		};
	};

	clocks: clock-controller@4c000000 {
		compatible = "samsung,s3c2416-clock";
		reg = <0x4c000000 0x40>;
		#clock-cells = <1>;
	};

	uart_3: serial@5000c000 {
		compatible = "samsung,s3c2440-uart";
		reg = <0x5000C000 0x4000>;
		interrupts = <1 18 24 4>, <1 18 25 4>;
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
				<&clocks SCLK_UART>;
		status = "disabled";
	};

	sdhci_1: sdhci@4ac00000 {
		compatible = "samsung,s3c6410-sdhci";
		reg = <0x4AC00000 0x100>;
		interrupts = <0 0 21 3>;
		clock-names = "hsmmc", "mmc_busclk.0",
				"mmc_busclk.2";
		clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
				<&clocks MUX_HSMMC0>;
		status = "disabled";
	};

	sdhci_0: sdhci@4a800000 {
		compatible = "samsung,s3c6410-sdhci";
		reg = <0x4A800000 0x100>;
		interrupts = <0 0 20 3>;
		clock-names = "hsmmc", "mmc_busclk.0",
				"mmc_busclk.2";
		clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
				<&clocks MUX_HSMMC1>;
		status = "disabled";
	};
};

&i2c {
	compatible = "samsung,s3c2440-i2c";
	clocks = <&clocks PCLK_I2C0>;
	clock-names = "i2c";
};

&intc {
	compatible = "samsung,s3c2416-irq";
};

&pinctrl_0 {
	compatible = "samsung,s3c2416-pinctrl";
};

&rtc {
	compatible = "samsung,s3c2416-rtc";
	clocks = <&clocks PCLK_RTC>;
	clock-names = "rtc";
};

&timer {
	clocks = <&clocks PCLK_PWM>;
	clock-names = "timers";
};

&uart_0 {
	compatible = "samsung,s3c2440-uart";
	clock-names = "uart", "clk_uart_baud2",
			"clk_uart_baud3";
	clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
			<&clocks SCLK_UART>;
};

&uart_1 {
	compatible = "samsung,s3c2440-uart";
	clock-names = "uart", "clk_uart_baud2",
			"clk_uart_baud3";
	clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
			<&clocks SCLK_UART>;
};

&uart_2 {
	compatible = "samsung,s3c2440-uart";
	clock-names = "uart", "clk_uart_baud2",
			"clk_uart_baud3";
	clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
			<&clocks SCLK_UART>;
};

&watchdog {
	interrupts = <1 9 27 3>;
	clocks = <&clocks PCLK_WDT>;
	clock-names = "watchdog";
};