| // SPDX-License-Identifier: GPL-2.0 |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/thermal/thermal.h> |
| #include "tegra30.dtsi" |
| #include "tegra30-cpu-opp.dtsi" |
| #include "tegra30-cpu-opp-microvolt.dtsi" |
| |
| /** |
| * This file contains common DT entry for all fab version of Cardhu. |
| * There is multiple fab version of Cardhu starting from A01 to A07. |
| * Cardhu fab version A01 and A03 are not supported. Cardhu fab version |
| * A02 will have different sets of GPIOs for fixed regulator compare to |
| * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are |
| * compatible with fab version A04. Based on Cardhu fab version, the |
| * related dts file need to be chosen like for Cardhu fab version A02, |
| * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use |
| * tegra30-cardhu-a04.dts. |
| * The identification of board is done in two ways, by looking the sticker |
| * on PCB and by reading board id eeprom. |
| * The sticker will have number like 600-81291-1000-002 C.3. In this 4th |
| * number is the fab version like here it is 002 and hence fab version A02. |
| * The (downstream internal) U-Boot of Cardhu display the board-id as |
| * follows: |
| * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00 |
| * In this Fab version is 02 i.e. A02. |
| * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56). |
| * The location 0x8 of this eeprom contains the Fab version. It is 1 byte |
| * wide. |
| */ |
| |
| / { |
| model = "NVIDIA Tegra30 Cardhu evaluation board"; |
| compatible = "nvidia,cardhu", "nvidia,tegra30"; |
| |
| aliases { |
| rtc0 = "/i2c@7000d000/tps65911@2d"; |
| rtc1 = "/rtc@7000e000"; |
| serial0 = &uarta; |
| serial1 = &uartc; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@80000000 { |
| reg = <0x80000000 0x40000000>; |
| }; |
| |
| pcie@3000 { |
| status = "okay"; |
| |
| /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */ |
| avdd-pexb-supply = <&ldo1_reg>; |
| vdd-pexb-supply = <&ldo1_reg>; |
| avdd-pex-pll-supply = <&ldo1_reg>; |
| hvdd-pex-supply = <&pex_hvdd_3v3_reg>; |
| vddio-pex-ctl-supply = <&sys_3v3_reg>; |
| avdd-plle-supply = <&ldo2_reg>; |
| |
| pci@1,0 { |
| nvidia,num-lanes = <4>; |
| }; |
| |
| pci@2,0 { |
| nvidia,num-lanes = <1>; |
| }; |
| |
| pci@3,0 { |
| status = "okay"; |
| nvidia,num-lanes = <1>; |
| }; |
| }; |
| |
| host1x@50000000 { |
| dc@54200000 { |
| rgb { |
| status = "okay"; |
| |
| nvidia,panel = <&panel>; |
| }; |
| }; |
| }; |
| |
| pinmux@70000868 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&state_default>; |
| |
| state_default: pinmux { |
| sdmmc1_clk_pz0 { |
| nvidia,pins = "sdmmc1_clk_pz0"; |
| nvidia,function = "sdmmc1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_cmd_pz1 { |
| nvidia,pins = "sdmmc1_cmd_pz1", |
| "sdmmc1_dat0_py7", |
| "sdmmc1_dat1_py6", |
| "sdmmc1_dat2_py5", |
| "sdmmc1_dat3_py4"; |
| nvidia,function = "sdmmc1"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_clk_pa6 { |
| nvidia,pins = "sdmmc3_clk_pa6"; |
| nvidia,function = "sdmmc3"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_cmd_pa7 { |
| nvidia,pins = "sdmmc3_cmd_pa7", |
| "sdmmc3_dat0_pb7", |
| "sdmmc3_dat1_pb6", |
| "sdmmc3_dat2_pb5", |
| "sdmmc3_dat3_pb4"; |
| nvidia,function = "sdmmc3"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc4_clk_pcc4 { |
| nvidia,pins = "sdmmc4_clk_pcc4", |
| "sdmmc4_rst_n_pcc3"; |
| nvidia,function = "sdmmc4"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc4_dat0_paa0 { |
| nvidia,pins = "sdmmc4_dat0_paa0", |
| "sdmmc4_dat1_paa1", |
| "sdmmc4_dat2_paa2", |
| "sdmmc4_dat3_paa3", |
| "sdmmc4_dat4_paa4", |
| "sdmmc4_dat5_paa5", |
| "sdmmc4_dat6_paa6", |
| "sdmmc4_dat7_paa7"; |
| nvidia,function = "sdmmc4"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dap2_fs_pa2 { |
| nvidia,pins = "dap2_fs_pa2", |
| "dap2_sclk_pa3", |
| "dap2_din_pa4", |
| "dap2_dout_pa5"; |
| nvidia,function = "i2s1"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdio3 { |
| nvidia,pins = "drive_sdio3"; |
| nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,pull-down-strength = <46>; |
| nvidia,pull-up-strength = <42>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; |
| }; |
| uart3_txd_pw6 { |
| nvidia,pins = "uart3_txd_pw6", |
| "uart3_cts_n_pa1", |
| "uart3_rts_n_pc0", |
| "uart3_rxd_pw7"; |
| nvidia,function = "uartc"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| }; |
| }; |
| |
| serial@70006000 { |
| status = "okay"; |
| }; |
| |
| serial@70006200 { |
| compatible = "nvidia,tegra30-hsuart"; |
| status = "okay"; |
| }; |
| |
| pwm@7000a000 { |
| status = "okay"; |
| }; |
| |
| panelddc: i2c@7000c000 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@7000c400 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@7000c500 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| |
| /* ALS and Proximity sensor */ |
| isl29028@44 { |
| compatible = "isil,isl29028"; |
| reg = <0x44>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| i2cmux@70 { |
| compatible = "nxp,pca9546"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70>; |
| reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| i2c@7000c700 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@7000d000 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| |
| wm8903: wm8903@1a { |
| compatible = "wlf,wm8903"; |
| reg = <0x1a>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| micdet-cfg = <0>; |
| micdet-delay = <100>; |
| gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
| }; |
| |
| pmic: tps65911@2d { |
| compatible = "ti,tps65911"; |
| reg = <0x2d>; |
| |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| wakeup-source; |
| |
| ti,system-power-controller; |
| |
| #gpio-cells = <2>; |
| gpio-controller; |
| |
| vcc1-supply = <&vdd_ac_bat_reg>; |
| vcc2-supply = <&vdd_ac_bat_reg>; |
| vcc3-supply = <&vio_reg>; |
| vcc4-supply = <&vdd_5v0_reg>; |
| vcc5-supply = <&vdd_ac_bat_reg>; |
| vcc6-supply = <&vdd2_reg>; |
| vcc7-supply = <&vdd_ac_bat_reg>; |
| vccio-supply = <&vdd_ac_bat_reg>; |
| |
| regulators { |
| vdd1_reg: vdd1 { |
| regulator-name = "vddio_ddr_1v2"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-always-on; |
| }; |
| |
| vdd2_reg: vdd2 { |
| regulator-name = "vdd_1v5_gen"; |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1500000>; |
| regulator-always-on; |
| }; |
| |
| vddctrl_reg: vddctrl { |
| regulator-name = "vdd_cpu,vdd_sys"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1250000>; |
| regulator-coupled-with = <&vdd_core>; |
| regulator-coupled-max-spread = <300000>; |
| regulator-max-step-microvolt = <100000>; |
| regulator-always-on; |
| |
| nvidia,tegra-cpu-regulator; |
| }; |
| |
| vio_reg: vio { |
| regulator-name = "vdd_1v8_gen"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: ldo1 { |
| regulator-name = "vdd_pexa,vdd_pexb"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| }; |
| |
| ldo2_reg: ldo2 { |
| regulator-name = "vdd_sata,avdd_plle"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| }; |
| |
| /* LDO3 is not connected to anything */ |
| |
| ldo4_reg: ldo4 { |
| regulator-name = "vdd_rtc"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-always-on; |
| }; |
| |
| ldo5_reg: ldo5 { |
| regulator-name = "vddio_sdmmc,avdd_vdac"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| ldo6_reg: ldo6 { |
| regulator-name = "avdd_dsi_csi,pwrdet_mipi"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| }; |
| |
| ldo7_reg: ldo7 { |
| regulator-name = "vdd_pllm,x,u,a_p_c_s"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-always-on; |
| }; |
| |
| ldo8_reg: ldo8 { |
| regulator-name = "vdd_ddr_hs"; |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <1000000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| nct1008: temperature-sensor@4c { |
| compatible = "onnn,nct1008"; |
| reg = <0x4c>; |
| vcc-supply = <&sys_3v3_reg>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| vdd_core: tps62361@60 { |
| compatible = "ti,tps62361"; |
| reg = <0x60>; |
| |
| regulator-name = "tps62361-vout"; |
| regulator-min-microvolt = <500000>; |
| regulator-max-microvolt = <1500000>; |
| regulator-coupled-with = <&vddctrl_reg>; |
| regulator-coupled-max-spread = <300000>; |
| regulator-max-step-microvolt = <100000>; |
| regulator-boot-on; |
| regulator-always-on; |
| ti,vsel0-state-high; |
| ti,vsel1-state-high; |
| |
| nvidia,tegra-core-regulator; |
| }; |
| }; |
| |
| spi@7000da00 { |
| status = "okay"; |
| spi-max-frequency = <25000000>; |
| spi-flash@1 { |
| compatible = "winbond,w25q32", "jedec,spi-nor"; |
| reg = <1>; |
| spi-max-frequency = <20000000>; |
| }; |
| }; |
| |
| pmc@7000e400 { |
| status = "okay"; |
| nvidia,invert-interrupt; |
| nvidia,suspend-mode = <1>; |
| nvidia,cpu-pwr-good-time = <2000>; |
| nvidia,cpu-pwr-off-time = <200>; |
| nvidia,core-pwr-good-time = <3845 3845>; |
| nvidia,core-pwr-off-time = <0>; |
| nvidia,core-power-req-active-high; |
| nvidia,sys-clock-req-active-high; |
| }; |
| |
| ahub@70080000 { |
| i2s@70080400 { |
| status = "okay"; |
| }; |
| }; |
| |
| mmc@78000000 { |
| status = "okay"; |
| cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; |
| power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; |
| bus-width = <4>; |
| }; |
| |
| mmc@78000600 { |
| status = "okay"; |
| bus-width = <8>; |
| non-removable; |
| }; |
| |
| usb@7d008000 { |
| status = "okay"; |
| }; |
| |
| usb-phy@7d008000 { |
| vbus-supply = <&usb3_vbus_reg>; |
| status = "okay"; |
| }; |
| |
| backlight: backlight { |
| compatible = "pwm-backlight"; |
| |
| enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| power-supply = <&vdd_bl_reg>; |
| pwms = <&pwm 0 5000000>; |
| |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| }; |
| |
| clk32k_in: clock@0 { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| #clock-cells = <0>; |
| }; |
| |
| cpus { |
| cpu0: cpu@0 { |
| cpu-supply = <&vddctrl_reg>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@1 { |
| cpu-supply = <&vddctrl_reg>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu2: cpu@2 { |
| cpu-supply = <&vddctrl_reg>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu3: cpu@3 { |
| cpu-supply = <&vddctrl_reg>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| #cooling-cells = <2>; |
| }; |
| }; |
| |
| panel: panel { |
| compatible = "chunghwa,claa101wb01"; |
| ddc-i2c-bus = <&panelddc>; |
| |
| power-supply = <&vdd_pnl1_reg>; |
| enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; |
| |
| backlight = <&backlight>; |
| }; |
| |
| vdd_ac_bat_reg: regulator@0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_ac_bat"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-always-on; |
| }; |
| |
| cam_1v8_reg: regulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "cam_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&vio_reg>; |
| }; |
| |
| cp_5v_reg: regulator@2 { |
| compatible = "regulator-fixed"; |
| regulator-name = "cp_5v"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| enable-active-high; |
| gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| emmc_3v3_reg: regulator@3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "emmc_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| modem_3v3_reg: regulator@4 { |
| compatible = "regulator-fixed"; |
| regulator-name = "modem_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; |
| }; |
| |
| pex_hvdd_3v3_reg: regulator@5 { |
| compatible = "regulator-fixed"; |
| regulator-name = "pex_hvdd_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_cam1_ldo_reg: regulator@6 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_cam1_ldo"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_cam2_ldo_reg: regulator@7 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_cam2_ldo"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_cam3_ldo_reg: regulator@8 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_cam3_ldo"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_com_reg: regulator@9 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_com"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_fuse_3v3_reg: regulator@10 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_fuse_3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_pnl1_reg: regulator@11 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vdd_pnl1"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; |
| vin-supply = <&sys_3v3_reg>; |
| }; |
| |
| vdd_vid_reg: regulator@12 { |
| compatible = "regulator-fixed"; |
| regulator-name = "vddio_vid"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| enable-active-high; |
| gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; |
| gpio-open-drain; |
| vin-supply = <&vdd_5v0_reg>; |
| }; |
| |
| sound { |
| compatible = "nvidia,tegra-audio-wm8903-cardhu", |
| "nvidia,tegra-audio-wm8903"; |
| nvidia,model = "NVIDIA Tegra Cardhu"; |
| |
| nvidia,audio-routing = |
| "Headphone Jack", "HPOUTR", |
| "Headphone Jack", "HPOUTL", |
| "Int Spk", "ROP", |
| "Int Spk", "RON", |
| "Int Spk", "LOP", |
| "Int Spk", "LON", |
| "Mic Jack", "MICBIAS", |
| "IN1L", "Mic Jack"; |
| |
| nvidia,i2s-controller = <&tegra_i2s1>; |
| nvidia,audio-codec = <&wm8903>; |
| |
| nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
| GPIO_ACTIVE_LOW>; |
| |
| clocks = <&tegra_car TEGRA30_CLK_PLL_A>, |
| <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, |
| <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
| clock-names = "pll_a", "pll_a_out0", "mclk"; |
| |
| assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, |
| <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
| |
| assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, |
| <&tegra_car TEGRA30_CLK_EXTERN1>; |
| }; |
| |
| thermal-zones { |
| cpu-thermal { |
| polling-delay-passive = <1000>; /* milliseconds */ |
| polling-delay = <5000>; /* milliseconds */ |
| |
| thermal-sensors = <&nct1008 1>; |
| |
| trips { |
| trip0: cpu-alert0 { |
| /* throttle at 57C until temperature drops to 56.8C */ |
| temperature = <57000>; |
| hysteresis = <200>; |
| type = "passive"; |
| }; |
| |
| trip1: cpu-crit { |
| /* shut down at 60C */ |
| temperature = <60000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&trip0>; |
| cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| |
| power { |
| label = "Power"; |
| interrupt-parent = <&pmic>; |
| interrupts = <2 0>; |
| linux,code = <KEY_POWER>; |
| debounce-interval = <100>; |
| wakeup-source; |
| }; |
| |
| volume-down { |
| label = "Volume Down"; |
| gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_VOLUMEDOWN>; |
| debounce-interval = <10>; |
| }; |
| |
| volume-up { |
| label = "Volume Up"; |
| gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_VOLUMEUP>; |
| debounce-interval = <10>; |
| }; |
| }; |
| }; |
