| // SPDX-License-Identifier: GPL-2.0 |
| /* Copyright(c) 2009-2014 Realtek Corporation.*/ |
| |
| #include "../wifi.h" |
| #include "reg.h" |
| #include "def.h" |
| #include "phy.h" |
| #include "rf.h" |
| #include "dm.h" |
| |
| static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw); |
| |
| void rtl92ee_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) |
| { |
| struct rtl_priv *rtlpriv = rtl_priv(hw); |
| struct rtl_phy *rtlphy = &rtlpriv->phy; |
| |
| switch (bandwidth) { |
| case HT_CHANNEL_WIDTH_20: |
| rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & |
| 0xfffff3ff) | BIT(10) | BIT(11)); |
| rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, |
| rtlphy->rfreg_chnlval[0]); |
| rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, |
| rtlphy->rfreg_chnlval[0]); |
| break; |
| case HT_CHANNEL_WIDTH_20_40: |
| rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & |
| 0xfffff3ff) | BIT(10)); |
| rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, |
| rtlphy->rfreg_chnlval[0]); |
| rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, |
| rtlphy->rfreg_chnlval[0]); |
| break; |
| default: |
| pr_err("unknown bandwidth: %#X\n", bandwidth); |
| break; |
| } |
| } |
| |
| bool rtl92ee_phy_rf6052_config(struct ieee80211_hw *hw) |
| { |
| struct rtl_priv *rtlpriv = rtl_priv(hw); |
| struct rtl_phy *rtlphy = &rtlpriv->phy; |
| |
| if (rtlphy->rf_type == RF_1T1R) |
| rtlphy->num_total_rfpath = 1; |
| else |
| rtlphy->num_total_rfpath = 2; |
| |
| return _rtl92ee_phy_rf6052_config_parafile(hw); |
| } |
| |
| static bool _rtl92ee_phy_rf6052_config_parafile(struct ieee80211_hw *hw) |
| { |
| struct rtl_priv *rtlpriv = rtl_priv(hw); |
| struct rtl_phy *rtlphy = &rtlpriv->phy; |
| u32 u4_regvalue = 0; |
| u8 rfpath; |
| bool rtstatus = true; |
| struct bb_reg_def *pphyreg; |
| |
| for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { |
| pphyreg = &rtlphy->phyreg_def[rfpath]; |
| |
| switch (rfpath) { |
| case RF90_PATH_A: |
| case RF90_PATH_C: |
| u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, |
| BRFSI_RFENV); |
| break; |
| case RF90_PATH_B: |
| case RF90_PATH_D: |
| u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, |
| BRFSI_RFENV << 16); |
| break; |
| } |
| |
| rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); |
| udelay(1); |
| |
| rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); |
| udelay(1); |
| |
| rtl_set_bbreg(hw, pphyreg->rfhssi_para2, |
| B3WIREADDREAALENGTH, 0x0); |
| udelay(1); |
| |
| rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); |
| udelay(1); |
| |
| switch (rfpath) { |
| case RF90_PATH_A: |
| rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw, |
| (enum radio_path)rfpath); |
| break; |
| case RF90_PATH_B: |
| rtstatus = rtl92ee_phy_config_rf_with_headerfile(hw, |
| (enum radio_path)rfpath); |
| break; |
| case RF90_PATH_C: |
| break; |
| case RF90_PATH_D: |
| break; |
| } |
| |
| switch (rfpath) { |
| case RF90_PATH_A: |
| case RF90_PATH_C: |
| rtl_set_bbreg(hw, pphyreg->rfintfs, |
| BRFSI_RFENV, u4_regvalue); |
| break; |
| case RF90_PATH_B: |
| case RF90_PATH_D: |
| rtl_set_bbreg(hw, pphyreg->rfintfs, |
| BRFSI_RFENV << 16, u4_regvalue); |
| break; |
| } |
| |
| if (!rtstatus) { |
| rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, |
| "Radio[%d] Fail!!\n", rfpath); |
| return false; |
| } |
| } |
| |
| rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n"); |
| return rtstatus; |
| } |