| # SPDX-License-Identifier: GPL-2.0 |
| obj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o |
| obj-$(CONFIG_ARM_CCN) += arm-ccn.o |
| obj-$(CONFIG_ARM_CMN) += arm-cmn.o |
| obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o |
| obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o |
| obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o |
| obj-$(CONFIG_ARM_PMUV3) += arm_pmuv3.o |
| obj-$(CONFIG_ARM_SMMU_V3_PMU) += arm_smmuv3_pmu.o |
| obj-$(CONFIG_FSL_IMX8_DDR_PMU) += fsl_imx8_ddr_perf.o |
| obj-$(CONFIG_FSL_IMX9_DDR_PMU) += fsl_imx9_ddr_perf.o |
| obj-$(CONFIG_HISI_PMU) += hisilicon/ |
| obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o |
| obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o |
| obj-$(CONFIG_RISCV_PMU) += riscv_pmu.o |
| obj-$(CONFIG_RISCV_PMU_LEGACY) += riscv_pmu_legacy.o |
| obj-$(CONFIG_RISCV_PMU_SBI) += riscv_pmu_sbi.o |
| obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o |
| obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o |
| obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o |
| obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o |
| obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o |
| obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o |
| obj-$(CONFIG_APPLE_M1_CPU_PMU) += apple_m1_cpu_pmu.o |
| obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) += alibaba_uncore_drw_pmu.o |
| obj-$(CONFIG_DWC_PCIE_PMU) += dwc_pcie_pmu.o |
| obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu/ |
| obj-$(CONFIG_MESON_DDR_PMU) += amlogic/ |
| obj-$(CONFIG_CXL_PMU) += cxl_pmu.o |
