| [ | |
| { | |
| "ArchStdEvent": "CPU_CYCLES" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_CYCLES" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS_RD" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS_WR" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS_SHARED" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS_NORMAL" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS_PERIPH" | |
| }, | |
| { | |
| "ArchStdEvent": "BUS_ACCESS" | |
| }, | |
| { | |
| "ArchStdEvent": "CNT_CYCLES" | |
| } | |
| ] |