| [ |
| { |
| "ArchStdEvent": "LD_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "MEM_ACCESS_RD" |
| }, |
| { |
| "ArchStdEvent": "MEM_ACCESS_WR" |
| }, |
| { |
| "ArchStdEvent": "UNALIGNED_LD_SPEC" |
| }, |
| { |
| "ArchStdEvent": "UNALIGNED_ST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "UNALIGNED_LDST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LD_ALIGN_LAT" |
| }, |
| { |
| "ArchStdEvent": "ST_ALIGN_LAT" |
| }, |
| { |
| "ArchStdEvent": "MEM_ACCESS" |
| }, |
| { |
| "ArchStdEvent": "MEMORY_ERROR" |
| }, |
| { |
| "ArchStdEvent": "LDST_ALIGN_LAT" |
| }, |
| { |
| "ArchStdEvent": "MEM_ACCESS_CHECKED" |
| }, |
| { |
| "ArchStdEvent": "MEM_ACCESS_CHECKED_RD" |
| }, |
| { |
| "ArchStdEvent": "MEM_ACCESS_CHECKED_WR" |
| } |
| ] |
