| # SPDX-License-Identifier: GPL-2.0 |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/spi/spi-controller.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: SPI Controller Generic Binding |
| |
| maintainers: |
| - Mark Brown <broonie@kernel.org> |
| |
| description: | |
| SPI busses can be described with a node for the SPI controller device |
| and a set of child nodes for each SPI slave on the bus. The system SPI |
| controller may be described for use in SPI master mode or in SPI slave mode, |
| but not for both at the same time. |
| |
| properties: |
| $nodename: |
| pattern: "^spi(@.*|-[0-9a-f])*$" |
| |
| "#address-cells": |
| enum: [0, 1] |
| |
| "#size-cells": |
| const: 0 |
| |
| cs-gpios: |
| description: | |
| GPIOs used as chip selects. |
| If that property is used, the number of chip selects will be |
| increased automatically with max(cs-gpios, hardware chip selects). |
| |
| So if, for example, the controller has 4 CS lines, and the |
| cs-gpios looks like this |
| cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; |
| |
| Then it should be configured so that num_chipselect = 4, with |
| the following mapping |
| cs0 : &gpio1 0 0 |
| cs1 : native |
| cs2 : &gpio1 1 0 |
| cs3 : &gpio1 2 0 |
| |
| The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0) |
| or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0. |
| |
| There is a special rule set for combining the second flag of an |
| cs-gpio with the optional spi-cs-high flag for SPI slaves. |
| |
| Each table entry defines how the CS pin is to be physically |
| driven (not considering potential gpio inversions by pinmux): |
| |
| device node | cs-gpio | CS pin state active | Note |
| ================+===============+=====================+===== |
| spi-cs-high | - | H | |
| - | - | L | |
| spi-cs-high | ACTIVE_HIGH | H | |
| - | ACTIVE_HIGH | L | 1 |
| spi-cs-high | ACTIVE_LOW | H | 2 |
| - | ACTIVE_LOW | L | |
| |
| Notes: |
| 1) Should print a warning about polarity inversion. |
| Here it would be wise to avoid and define the gpio as |
| ACTIVE_LOW. |
| 2) Should print a warning about polarity inversion |
| because ACTIVE_LOW is overridden by spi-cs-high. |
| Should be generally avoided and be replaced by |
| spi-cs-high + ACTIVE_HIGH. |
| |
| num-cs: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| Total number of chip selects. |
| |
| spi-slave: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: |
| The SPI controller acts as a slave, instead of a master. |
| |
| allOf: |
| - if: |
| not: |
| required: |
| - spi-slave |
| then: |
| properties: |
| "#address-cells": |
| const: 1 |
| else: |
| properties: |
| "#address-cells": |
| const: 0 |
| |
| patternProperties: |
| "^slave$": |
| type: object |
| |
| properties: |
| compatible: |
| description: |
| Compatible of the SPI device. |
| |
| required: |
| - compatible |
| |
| "^.*@[0-9a-f]+$": |
| type: object |
| |
| properties: |
| compatible: |
| description: |
| Compatible of the SPI device. |
| |
| reg: |
| minimum: 0 |
| maximum: 256 |
| description: |
| Chip select used by the device. |
| |
| spi-3wire: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: |
| The device requires 3-wire mode. |
| |
| spi-cpha: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: |
| The device requires shifted clock phase (CPHA) mode. |
| |
| spi-cpol: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: |
| The device requires inverse clock polarity (CPOL) mode. |
| |
| spi-cs-high: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: |
| The device requires the chip select active high. |
| |
| spi-lsb-first: |
| $ref: /schemas/types.yaml#/definitions/flag |
| description: |
| The device requires the LSB first mode. |
| |
| spi-max-frequency: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| Maximum SPI clocking speed of the device in Hz. |
| |
| spi-rx-bus-width: |
| description: |
| Bus width to the SPI bus used for read transfers. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: [1, 2, 4, 8] |
| default: 1 |
| |
| spi-rx-delay-us: |
| description: |
| Delay, in microseconds, after a read transfer. |
| |
| spi-tx-bus-width: |
| description: |
| Bus width to the SPI bus used for write transfers. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| enum: [1, 2, 4, 8] |
| default: 1 |
| |
| spi-tx-delay-us: |
| description: |
| Delay, in microseconds, after a write transfer. |
| |
| required: |
| - compatible |
| - reg |
| |
| additionalProperties: true |
| |
| examples: |
| - | |
| spi@f00 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| reg = <0xf00 0x20>; |
| interrupts = <2 13 0 2 14 0>; |
| interrupt-parent = <&mpc5200_pic>; |
| |
| ethernet-switch@0 { |
| compatible = "micrel,ks8995m"; |
| spi-max-frequency = <1000000>; |
| reg = <0>; |
| }; |
| |
| codec@1 { |
| compatible = "ti,tlv320aic26"; |
| spi-max-frequency = <100000>; |
| reg = <1>; |
| }; |
| }; |